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Número de pieza | RMPA1963 | |
Descripción | CDMA2000-1X and WCDMA Power Amplifier Module | |
Fabricantes | Fairchild Semiconductor | |
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PRELIMINARY
May 2005
RMPA1963 i-Lo™
US-PCS CDMA, CDMA2000-1X and WCDMA
Power Amplifier Module
Features
■ 38% CDMA/WCDMA efficiency at +28 dBm Pout
■ 14% CDMA/WCDMA efficiency (85 mA total current) at
+16 dBm Pout
■ Meets HSDPA performance requirements
■ Linear operation in low-power mode up to +19 dBm
■ Low quiescent current (Iccq): 25 mA in low-power mode
■ Single positive-supply operation with low power and shut-
down modes
• 3.4V typical Vcc operation
• Low Vref (2.85V) compatible with advanced handset
chipsets
■ Compact Lead-free compliant LCC package –
(4.0 X 4.0 x 1.5 mm nominal)
■ Industry standard pinout
■ Internally matched to 50 Ohms and DC blocked RF
input/output
■ Meets IS-95/CDMA2000-1XRTT/WCDMA performance
requirements
General Description
The RMPA1963 Power Amplifier Module (PAM) is Fairchild’s lat-
est innovation in 50 Ohm matched, surface mount modules tar-
geting US-PCS CDMA/WCDMA/HSDPA and Wireless Local
Loop (WLL) applications. Answering the call for ultra-low DC
power consumption and extended battery life in portable elec-
tronics, the RMPA1963 uses novel proprietary circuitry to dra-
matically reduce amplifier current at low to medium RF output
power levels (< +16 dBm), where the handset most often oper-
ates. A simple two-state Vmode control is all that is needed to
reduce operating current by more than 50% at 16 dBm output
power, and quiescent current (Iccq) by as much as 70% com-
pared to traditional power-saving methods. No additional cir-
cuitry, such as DC-to-DC converters, are required to achieve
this remarkable improvement in amplifier efficiency. Further, the
4x4x1.5 mm LCC package is pin-compatible and a drop-in
replacement for last generation 4x4 mm PAMs widely used
today, minimizing the design time to apply this performance-
enhancing technology. The multi-stage GaAs Microwave Mono-
lithic Integrated Circuit (MMIC) is manufactured using Fairchild
RF’s InGaP Heterojunction Bipolar Transistor (HBT) process.
Device
i-L
o
™
Functional Block Diagram
(Top View)
Vcc1 1
RF IN 2
GND 3
Vmode 4
Vref 5
MMIC
INPUT
MATCH
BIAS/MODE SWITCH
10 Vcc2
OUTPUT
MATCH
9 GND
8 RF OUT
7 GND
6 GND
11 (paddle ground on package bottom)
©2005 Fairchild Semiconductor Corporation
RMPA1963 i-Lo™ Rev. H
1
www.fairchildsemi.com
1 page Package Outline
I/O 1 INDICATOR
1
(4.00mm
+.100
–.050
)
SQUARE
2
3
4
5
TOP VIEW
10
9
8
7
6
1.60mm MAX.
.25mm TYP.
FRONT VIEW
3.50mm TYP.
See Detail A
.30mm TYP.
.85mm TYP.
2
11
1
1.08mm
1.84mm
BOTTOM VIEW
3.65mm
.18mm
Signal Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
Signal Name
Vcc1
RF In
GND
Vmode
Vref
GND
GND
RF Out
GND
Vcc2
GND
Description
Supply Voltage to Input Stage
RF Input Signal
Ground
High Power/Low Power Mode Control
Reference Voltage
Ground
Ground
RF Output Signal
Ground
Supply Voltage to Output Stage
Paddle Ground
.40mm
.10mm
.10mm
.40mm
.45mm
DETAIL A. TYP.
i-L
o
™
RMPA1963 i-Lo™ Rev. H
5
www.fairchildsemi.com
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet RMPA1963.PDF ] |
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