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PDF W83194BR-645 Data sheet ( Hoja de datos )
| Número de pieza | W83194BR-645 | |
| Descripción | CLOCK GENERATOR | |
| Fabricantes | Winbond | |
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W83194BR-645
Data Sheet
WINBOND
CLOCK GENERATOR
FOR
SIS 645/650 CHIPSET
Publication Release Date: April 13, 2005
- I - Revision 2.1
1 page  
W83194BR-645
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL
IN
INtp120k
INtd120k
OUT
OD
I/O
I/OD
#
*
&
DESCRIPTION
Input
Latched input at power up, internal 120 KΩ pull up.
Latched input at power up, internal 120 KΩ pull down.
Output
Open Drain
Bi-directional Pin
Bi-directional Pin, Open Drain.
Active Low
Internal 120 KΩ pull-up
Internal 120 KΩ pull-down
5.1 Crystal I/O
PIN PIN NAME
6 XIN
7 XOUT
TYPE
IN
OUT
DESCRIPTION
Crystal input with internal loading capacitors (18pF) and
feedback resistors.
Crystal output at 14.318 MHz nominally with internal loading
capacitors (18pF).
5.2 CPU, ZCLK, SDRAM, PCI Clock Outputs
PIN
40, 39,
44, 43
47
14
15
16, 17, 20,
21, 22, 23
PIN NAME
CPUCLKT_0
CPUCLKC_0,
CPUCLKT_1
CPUCLKC_1,
SDRAM
PCICLK_F0
FS3&
PCICLK_F1
FS4&
PCICLK [0:5]
TYPE
OUT
OUT
OUT
INtd120k
OUT
INtd120k
OUT
DESCRIPTION
True CPU clock output and Complementary CPU clock output.
This pin will be stopped by CPU_STOP#
SDRAM clock output, which have syn. or asyn. Frequencies
as CPU clocks. The clock phase is the same as CPUCLKT_0
and CPUCLKT_1.
PCI free running clock during normal operation.
Latched input for FS3 at initial power up for H/W selecting the
output frequency. Internal 120KΩ pull-down
PCI free running clock during normal operation.
Latched input for FS4 at initial power up for H/W selecting the
output frequency. Internal 120KΩ pull-down
Low skew (< 500pS) PCI clock outputs.
Publication Release Date: April 13, 2005
- 3 - Revision 2.1
5 Page 
W83194BR-645
7. I2C CONTROL AND STATUS REGISTERS
The Register 0~3 are reserved for external clock buffer
(The register No. Is increased by 1 if use byte data read/write protocol)
7.1 Register 4: Frequency Select Register (default = 0)
BIT
NAME
PWD
DESCRIPTION
7 SSEL [3] 0
6 SSEL [2] 0 Frequency selection by software via I2C
5 SSEL [1] 0
4 SSEL [0] 0
Enable software program FS [4:0].
3 EN_SSEL 0 0 = Select frequency by hardware.
1= Select frequency by software I2C - Bit 4: 7, 2.
2 SSEL [4] 0 Frequency selection bit 4
Enable Spread Spectrum in the frequency table.
1 EN_SPSP 0 0 = Normal
1 = Spread Spectrum enabled
Enable reload safe frequency when the watchdog is timeout.
0 EN_SAFE_FREQ 0 0 = reload the FS [4:0] latched pins when watchdog time out.
1 = reload the safe frequency bit defined at Register 9 bit 4~0.
7.2 Register 5: CPU, SDRAM Clock Register (1 = Enable, 0 = Stopped)
BIT
PIN NO.
PWD
DESCRIPTION
7 47 1 SDRAM
6 44, 43 1 CPUCLKT/C1
5 40, 39 1 CPUCLKT/C0
4 15 X FS [4] Read back.
3 14 X FS [3] Read back
2 4 X FS [2] Read back
1 3 X FS [1] Read back
0 2 X FS [0] Read back
Publication Release Date: April 13, 2005
- 9 - Revision 2.1
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet W83194BR-645.PDF ] | |
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