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W83194BR-640 데이터시트 PDF




Winbond에서 제조한 전자 부품 W83194BR-640은 전자 산업 및 응용 분야에서
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부품번호 W83194BR-640 기능
기능 166MHZ CLOCK
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W83194BR-640 데이터시트, 핀배열, 회로
www.DataSheet4U.com
W83194BR-640
166MHZ CLOCK FOR SIS CHIPSET
W83194BR-640
Data Sheet Revision History
Pages
1 n.a.
2 n.a.
3
4
5
6
7
8
9
10
Dates Version
02/Apr
1.0
Version
On Web
n.a.
1.0
Main Contents
All of the versions before 0.50 are for internal use.
Change version and version on web site to 1.0
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Publication Release Date: April. 2001
- 1 - Revision 1.0




W83194BR-640 pdf, 반도체, 판매, 대치품
W83194BR-640
4.2 CPU, SDRAM, PCI Clock Outputs
SYMBOL
PIN I/O
FUNCTION
IOAPIC0
CPUCLK0T
CPUCLK0C
CPUCLK1T
SDRAM_out
PCICLK_F^/ &FS2
PCICLK 1^/ &FS3
PCICLK ^[2:5]
RESET#
47
44,43
40
35
9
10
12,13,15,16
37
OUT
OUT
OUT
OUT
I/O
I/O
OUT
OD
16.7/33MHz APIC clock for CPU and Chipset by I2C
byte 7 bit 3
True CPU clock output and Complementary CPU
clock output. This pin will be stopped by
CPU_STOP#
Low skew (< 250ps) clock outputs for host
CPU clock output for chipset and CPU,
When byte 9 bit 6 = 0
This pin will not be stopped by CPU_STOP#
SDRAM clock output which have syn. or asyn.
Frequencies as CPU clocks. The clock phase is the
same as CPUCLK0T and CPUCLK1T.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks. Internal 120Kpull-down
PCI free running clock during normal operation.
PCI output has 1.5X drive strength.
Latched input for FS3 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks. Internal 120Kpull-down
PCI clock during normal operation.
PCI output has 1.5X drive strength.
Low skew (< 250ps) PCI clock outputs.
PCI outputs have 1.5X drive strength.
Open Drain, 4ms low active pulse when Watch Dog
time out, the all clock output recover to hardware
FS0-FS3 setting.
4.3 I2C Control Interface
SYMBOL
*SDATA
*SDCLK
PIN I/O
FUNCTION
28 I/O Serial data of I2C 2-wire control interface
27 IN Serial clock of I2C 2-wire control interface
4.4 Fixed Frequency Outputs
SYMBOL
REF0^/&FS0
PIN
2
I/O FUNCTION
I/O 3.3V, 14.318MHz reference clock output. Internal
120kpull-down.This pin has 1.5X drive strength.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
Publication Release Date: April. 2001
- 4 - Revision 1.0

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W83194BR-640 전자부품, 판매, 대치품
W83194BR-640
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Set R/W to 1 when read back the data sequence is as follows, [1101 0011] :
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack Byte 1
Ack
Byte2, 3, 4...
until Stop
6.2 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power
up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte
Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in
these two bytes are considered "don't care", they must be sent and will be acknowledge. After that,
the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged.
6.2.1 Register 4: CPU Frequency Select Register (default = 0)
Bit @PowerUp
70
60
50
40
30
20
10
00
Pin Description
- SSEL3 (for frequency table selection by software via I2C)
- SSEL2 (for frequency table selection by software via I2C)
- SSEL1 (for frequency table selection by software via I2C)
- SSEL0 (for frequency table selection by software via I2C)
- 0 = Selection by hardware
1 = Selection by software I2C - Bit 1,2, 7:4
- SSEL4 (for frequency table selection by software via I2C)
- SSEL5 (for frequency table selection by software via I2C)
- 0 = Running
1 = Tri-state all outputs
Publication Release Date: April. 2001
- 7 - Revision 1.0

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