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U4091BM PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 U4091BM
기능 Programmable Telephone Audio Processor
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U4091BM 데이터시트, 핀배열, 회로
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Programmable Telephone Audio Processor
U4091BM
Description
The programmable telephone audio processor U4091BM
is a linear integrated circuit for use in feature phones,
answering machines and fax machines. It contains the
speech circuit, tone-ringer interface with DC/DC
converter, sidetone equivalent and ear-protection
rectifiers. The circuit is line-powered and contains all
components necessary for signal amplification and
adaptation to the line. The U4091BM can also be supplied
via an external power supply. An integrated voice switch
with loudspeaker amplifier enables hands-free or
loudhearing operation. With an anti-feedback function,
acoustical feedback during loudhearing can be reduced
significantly. The generated supply voltage is suitable for
a wide range of peripheral circuits.
Features
D Speech circuit with anti-clipping
D Tone-ringer interface with DC/DC converter
D Speaker amplifier with anti-distortion
D Power-supply management (regulated, unregulated)
and a special supply for electret microphone
D Voice switch
D Interface for answering machine and cordless phone
Benefits
D No piezoelectric transducer for tone ringing necessary
D Complete system integration of analog signal proces-
sing on one chip
D Very few external components
Applications
Feature phone, answering machine, fax machine, speaker
phone, cordless phone
Block Diagram
Speech
circuit
DTMF
Ordering Information
Extended Type Number
U4091BM-AFN
U4091BM-AFNG3
Voice
switch
Serial
bus
Audio
amplifier
Tone
ringer
Clock
Data
Reset
MCU
14601
Package
SSO44
SSO44
Remarks
Taped and reeled
Rev. A1, 02-Jun-98
Target Specification
1 (29)




U4091BM pdf, 반도체, 판매, 대치품
U4091BM
RECIN 1
44 STRC
TXACL 2
43 STC
MIC3 3
42 STO
MIC2 4
41 AMREC
MIC1 5
40 AMPB
RECO2 6
39 MICO
RECO1 7
38 IMPSW
IND 8
VL 9
SENSE 10
37 TLDT
36 INLDT
35 INLDR
GND 11
34 TLDR
VB 12
33 CT
SAO2 13
32 BNMT
SAO1 14
31 BNMR
VMPS 15
30 ADIN
VMP 16
29 ES
VMIC 17
28 RESET
TSACL 18
27 OSCOUT
VRING 19
IMPA 20
26 OSCIN
25 SDA
COSC 21
24 SCL
SWOUT 22
23 INT
14751
Figure 2. Pinning
DC Line Interface and
Supply-Voltage Generation
The DC line interface consists of an electronic inductance
and a dual-port output stage which charges the capacitors
at VMPS and VB. The value of the equivalent inductance
is given by:
L = 2 RSENSE CIND (RDC R30) / (RDC + R30)
The U4091BM contains two identical series regulators
which provide a supply voltage VMP of 3.3 V suitable for
a microprocessor. In speech mode, both regulators are
active because VMPS and VB are charged
simultaneously by the DC line interface. The output
current is 6 mA. The capacitor at VMPS is used to provide
the microcomputer with sufficient power during long line
interruptions. Thus, long flash pulses can be bridged or an
LCD display can be turned on for more than 2 seconds
after going on-hook. When the system is in ringing mode,
VB is charged by the on-chip ringing power converter. In
this mode, only one regulator is used to supply VMP with
maximum 3 mA.
Supply Structure of the Chip
A main benefit of the U4091BM is the easy implementa-
tion of various applications due to the flexible system
structure of the chip.
Possible applications:
D Group listening phone
D Hands-free phone
D Phones which feature ringing with the built-in speaker
amplifier
D Answering machine with external supply
The special supply topology for the various functional
blocks is illustrated in figure 3.
There are four major supply states:
1. Speech condition
2. Power down (pulse dialing)
3. Ringing
4. External supply
1. In speech condition, the system is supplied by the line
current. If the LIDET-block detects a line voltage
above approximately 2 V, the internal signal VLON is
activated. This is detected via the serial bus, all the
blocks which are needed have to be switched on via
the serial bus.
4 (29)
Rev. A1, 02-Jun-98
Target Specification

4페이지










U4091BM 전자부품, 판매, 대치품
U4091BM
CLOCK
Write cycle
DATA
D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 R/W=0
Data fromµP
Strobe
from µP
14574
Figure 4. Write cycle
CLOCK
Normal read cycle
DATA
A3 A2 A1 A0 R/W=1
Data fromµP
Strobe
from µP
D7 D6 D5 D4 D3 D2 D1 D0
Data from U4091B
14575
Figure 5. Normal read cycle
CLOCK
Fast read cycle
DATA
Strobe
from µP
D7=IZC D6=IVE
Data from U4091B
Figure 6. Fast read cycle
14576
Rev. A1, 02-Jun-98
Target Specification
7 (29)

7페이지



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Programmable Telephone Audio Processor

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TEMIC Semiconductors
U4091BM

Programmable Telephone Audio Processor

TEMIC Semiconductors
TEMIC Semiconductors

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