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W39V040A 데이터시트 PDF




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기능 512K X 8 CMOS FLASH MEMORY
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W39V040A 데이터시트, 핀배열, 회로
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W39V040A
512K × 8 CMOS FLASH MEMORY
WITH LPC INTERFACE
1. GENERAL DESCRIPTION
The W39V040A is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For
flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are
composed of 16 smaller even pages with 4 Kbytes. The device can be programmed and erased
in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture
of the W39V040A results in fast program/erase operations with extremely low current consumption. This
device can operate at two modes, Programmer bus interface mode and LPC bus interface mode. As in
the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs.
But in the LPC interface mode, this device complies with the Intel LPC specification. The device can also
be programmed and erased using standard EPROM programmers.
2. FEATURES
Single 3.3-volt Operations:
3.3-volt Read
3.3-volt Erase
3.3-volt Program
Fast Program Operation:
Byte-by-Byte programming: 35 µS (typ.)
Fast Erase Operation:
Chip erase 100 mS (max.)
Sector erase 25 mS (max.)
Page erase 25 mS (max.)
Fast Read access time: Tkq 11 nS
Endurance: 10K cycles (typ.)
Twenty-year data retention
8 Even sectors with 64K bytes each, which is
composed of 16 flexible pages with 4K bytes
Any individual sector or page can be erased
Hardware protection:
Optional 16K byte or 64K byte Top Boot Block
with lockout protection
#TBL & #WP support the whole chip hardware
protection
Flexible 4K-page size can be used as Parameter
Blocks
Low power consumption
Active current: 12.5 mA (typ. for LPC mode)
Automatic program and erase timing with
internal VPP generation
End of program or erase detection
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
Available packages: 32L PLCC, 32L STSOP
Publication Release Date: December 19, 2002
- 1 - Revision A2




W39V040A pdf, 반도체, 판매, 대치품
W39V040A
block, it will not partially lock the 16Kbytes boot block. You can check the DQ2/DQ3 at the address
7FFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is "0", it means the #TBL pin
is tied to high state. In such condition, whether boot block can be programmed/erased or not will depend
on software setting. On the other hand, if the DQ2 is "1", it means the #TBL pin is tied to low state, then
boot block is locked no matter how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP
state. If the DQ3 is "0", it means the #WP pin is in high state, then all the sectors except the boot block
can be programmed/erased. On the other hand, if the DQ3 is "1", then all the sectors except the boot
block are programmed/erased inhibited.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed
within fast 100 mS (max). The host system is not required to provide any control or timing during this
operation. If the boot block programming lockout is activated, only the data in the other memory sectors
will be erased to FF(hex) while the data in the boot block will not be erased (remains as the same state
before the chip erase operation). The entire memory array will be erased to FF(hex) by the chip erase
operation if the “boot block programming lockout feature” is not activated. The device will automatically
return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be
used to detect end of erase cycle.
Sector/Page Erase Operation
Sector/page erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing
the "set-up" command. Two more "unlock" write cycles then follows by the sector/page erase command.
The sector/page address (any address location within the desired sector/page) is latched on the rising
edge of R/C, while the command (30H/50H) is latched on the rising edge of #WE in programmer mode.
Sector/page erase does not require the user to program the device prior to erase. When erasing a
sector/page or sectors/pages the remaining unselected sectors/pages are not affected. The system is
not required to provide any controls or timings during these operations.
The automatic sector/page erase begins after the erase command is completed, right from the rising
edge of the #WE pulse for the last sector/page erase command pulse and terminates when the data on
DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be
performed at an address within any of the sectors/pages being erased.
Refer to the Erase Command flow Chart using typical command strings and bus operations.
Program Operation
The W39V040A is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot
block from "0" to "1", is needed before programming.
The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the
byte-program command is entered. The internal program timer will automatically time-out (50 µS max. -
TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be
used to detect end of program cycle.
-4-

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W39V040A 전자부품, 판매, 대치품
W39V040A
Continued
100
101
110
111
FFDF, FFFFh: FFD8, 0000h
FFD7, FFFFh: FFD0, 0000h
FFCF, FFFFh: FFC8, 0000h
FFC7, FFFFh: FFC0, 0000h
Table of Operating Modes
Operating Mode Selection - Programmer Mode
MODE
Read
Write
Standby
Write Inhibit
Output Disable
#OE
VIL
VIH
X
VIL
X
VIH
#WE
VIH
VIL
X
X
VIH
X
PINS
#RESET ADDRESS
VIH AIN
VIH AIN
VIL X
VIH X
VIH X
VIH X
DQ.
Dout
Din
High Z
High Z/DOUT
High Z/DOUT
High Z
Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "cycle type" when it is selected. When it is
not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory
Cycle Definition".
Standard LPC Memory Cycle Definition
FIELD
Start
Cycle Type & Dir
TAR
Addr.
Sync.
Data
NO. OF
CLOCKS
DESCRIPTION
1 "0000b" appears on LPC bus to indicate the initial
1
"010Xb" indicates memory read cycle; while "011xb" indicates memory write
cycle. "X" mean don't have to care.
2 Turned Around Time
Address Phase for Memory Cycle. LPC supports the 32 bits address protocol.
8 The addresses transfer most significant nibble first and least significant nibble
last. (i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.)
Synchronous to add wait state. "0000b" means Ready, "0101b" means Short
N Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error,
other values are reserved.
Data Phase for Memory Cycle. The data transfer least significant nibble first
2 and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4] on
LAD[3:0] last.)
Publication Release Date: December 19, 2002
- 7 - Revision A2

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