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PDF A6850 Data sheet ( Hoja de datos )
| Número de pieza | A6850 | |
| Descripción | Asynchronous Communications Interface Adapter | |
| Fabricantes | Altera Corporation | |
| Logotipo |  |
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September 1996, ver. 1
www.DataSheet4U.com
a6850
® Asynchronous Communications
Interface Adapter
Data Sheet
Features
General
Description
s a6850 MegaCore function implementing an asychronous
communications interface adapter (ACIA)
s Optimized for FLEX® and MAX® architectures
s Programmable word lengths, stop bits, and parity
s Offers divide-by-1, -16, or -64 mode
s Includes error detection
s Uses approximately 237 FLEX logic elements (LEs)
s Functionally based on the Motorola MC6850 device, except as noted
in the “Variations & Clarifications” section on page 94
The a6850 MegaCore function implements an ACIA, which is a universal
asynchronous receiver/transmitter (UART). The a6850 provides an
interface between a microprocessor and a serial communications channel.
The a6850 receives and transmits data in a variety of configurations,
including 7- or 8-bit data words, with odd, even, or no parity, and 1 or 2
stop bits. See Figure 1.
Figure 1. a6850 Symbol
nCTS
A6850
nDCD
E
nRESET
nIRQ
RS nRTS
RnW
TXDATA
RXCLK
DO[7..0]
RXDATA
TXCLK
CS[2..0]
DI[7..0]
Altera Corporation
A-DS-A6850-01
81
1 page  
a6850 Asynchronous Communications Interface Adapter Data Sheet
Table 3. Counter Divide Select Bits
cds1
0
0
1
1
cds0
0
1
0
1
Function
Divide-by-1 mode. Clock and data rate are identical. External
logic is responsible for synchronizing rxdata to rxclk. The
rxdata signal is sampled on the rising edge of rxclk, and
the txdata signal is asserted on the falling edge of txclk.
Divide-by-16 mode. The clock rate is 16 times the data rate.
After start bit detection (rxdata low), the rxdata signal is
sampled on the 9th rising edge of rxclk. After writing to the
transmitter data register, the txdata signal is asserted on
the first falling edge of txclk and every 16 clocks thereafter.
Divide-by-64 mode. The clock rate is 64 times the data rate.
After start bit detection (rxdata low), the rxdata signal is
sampled on the 33rd rising edge of rxclk. After writing to the
transmitter data register, the txdata signal is asserted on
the first falling edge of txclk and every 64 clocks thereafter.
Master reset. When master reset is selected, the a6850 is
reset to a known state; the status register is cleared, and the
transmit and receive operations are halted and initialized.
Word Select
Bits 2, 3, and 4 of the control register are the ws bits, which determine the
word length, parity, and number of stop bits. See Table 4.
Table 4. Word Select Bits
ws2 ws1 ws0
000
001
010
011
100
101
110
111
Word
Length
7
7
7
7
8
8
8
8
Stop Bits
2
2
1
1
2
1
1
1
Parity
Even
Odd
Even
Odd
None
None
Even
Odd
Altera Corporation
85
5 Page 
a6850 Asynchronous Communications Interface Adapter Data Sheet
Data Bit Sampling
After detecting a logic low, the a6850 samples and shifts the data into the
input shift register. Data bit sampling occurs on every rising edge in
divide-by-1 mode, every 16 rising edges in divide-by-16 mode, and every
64 rising edges in divide-by-64 mode. Each time a bit is sampled, parity is
calculated for future error detection. See Figure 4.
Figure 4. a6850 Receiver Functional Waveforms
Divide-by-1 Mode
rxclk
or txclk
rxdata
Sampled on rising edge of rxclk
txdata
Driven from falling edge of txclk
Divide-by-16 Mode
rxdata
rxclk
Sampling Pulse
txdata
txclk
Start Bit
Start Bit
Data Bit
Data Bit
Parity & Stop Bit Detection
The a6850 counts the number of data bits as it shifts. When the number of
data bits received matches the number specified in the control register, the
a6850 expects either a parity bit or a stop bit.
If parity is enabled, the a6850 samples for the parity bit, which is then
processed for parity. However, if parity is not enabled, the a6850 samples
for a stop bit (i.e., logic high). If a logic low is sampled, the fe bit is set in
the status register.
Altera Corporation
91
11 Page | ||
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