PDF M82C54-2 Data sheet ( Hoja de datos )

Número de pieza	M82C54-2
Descripción	CMOS PROGRAMMABLE INTERVAL TIMER
Fabricantes	OKI electronic
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No Preview Available ! E2O0019-27-X2 www.DataSheet4U.com ¡ Semiconductor¡ Semiconductor MThSiMs v8e2rCsi5o4n-:2JRaSn/. G19S9/8JS Previous version: Aug. 1996 MSM82C54-2RS/GS/JS CMOS PROGRAMMABLE INTERVAL TIMER GENERAL DESCRIPTION The MSM82C54-2RS/GS/JS is a programmable universal timer designed for use in microcomputer systems. Based on silicon gate CMOS technology, it requires a standby current of only 10 mA (max.) when the chip is in the non-selected state. And during timer operation, the power consumption is still very low with only 10mA (max.) of current required. It consists of three independent counters, and can count up to a maximum of 10 MHz. The timer features six different counter modes, and binary count/BCD count functions. Count values can be set in byte or word units, and all functions are freely programmable. FEATURES • Maximum operating frequency of 10 MHz (VCC=5 V) • High speed and low power consumption achieved by silicon gate CMOS technology • Completely static operation • Three independent 16-bit down-counters • Status Read Back Command • Six counter modes available for each counter • Binary and decimal counting possible • 24-pin Plastic DIP (DIP24-P-600-2.54): (Product name: MSM82C54-2RS) • 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C54-2JS) • 32-pin Plastic SSOP (SSOP32-P-430-1.00-K): (Product name: MSM82C54-2GS-K) 1/23 1 page ¡ Semiconductor MSM82C54-2RS/GS/JS AC CHARACTERISTICS Parameter Address Set-up Times to Falling Edge of RD Chip Select Input Set-up Time to Falling Edge of RD Address Hold Time from Rising Edge of RD RD Pulse Width Data Access Time from Falling Edge of RD Data Access Time after Address Determination Delay Time from Rising Edge of RD to Data Floting State RD Recovery Time Address Set-up Time to Falling Edge of WR Chip Select Input Set-up Time to Falling Edge of WR Address Hold Time from Rising Edge of WR WR Pulse Width Data Determination Set-up Time to Rising Edge of WR Data Hold Time after Rising Edge of WR WR Recovery Time CLK Cycle Time CLK "H" Level Width CLK "L" Level Width CLK Rise Time CLK Fall Time GATE "H" Level Width GATE "L" Level Width GATE Input Set-up Time before Rising Edge of CLK GATE Input Hold Time before Rising Edge of CLK Output Delay Time after Falling Edge of CLK Output Delay Time after Falling Edge of GATE CLK Rise Delay Time after Rising Edge of WR for Count Value Loading GATE sampling delay time after rising edge of WR for count loading Output Delay Time after Falling Edge of WR for Mode Set CLK Fall Set-up Time to Falling Edge of WR for Counter Latch Command (VCC = 4.5 V to 5.5 V, Ta = –40°C to +85°C) 82C54-2 Symbol Unit Conditions Min. Max. tAR 30 — ns tSR 0 — ns tRA 0 — ns tRR 95 — ns tRD — 94 ns tAD — 184 ns tDF 5 65 ns tRV 165 — ns tAW 0 — ns tSW 0 — ns tWA 0 — ns tWW 95 — ns tDW 85 — ns tWD 0 — ns tRV 165 — ns tCLK 100 D.C. ns tPWH 30 — ns tPWL 50 — ns tr — 25 ns tf — 25 ns tGW 50 — ns tGL 50 — ns tGS 40 — ns tGH 50 — ns tOD — 100 ns tODG — 100 ns CL = 150 pF tWC 0 55 ns tWG –5 40 ns tWO — 240 ns tCL –40 40 ns Note: Timing measured at VL = 0.8 V and VH = 2.2 V for both inputs and outputs. 5/23 5 Page ¡ Semiconductor Internal Block Diagram of a Counter Control Word Register Internal Data Bus Status Latch Status Register CRM MSM82C54-2RS/GS/JS CRL Control Logic CE GATEn CLKn OUTn OLM OLL NOTE : CRM : CRL : CE : OLM : OLL : Count Register MSB Count Register LSB Counter Element Output Latch MSB Output Latch LSB 11/23 11 Page

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