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TSA1204 데이터시트 PDF




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기능 A/D CONVERTER
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TSA1204 데이터시트, 핀배열, 회로
www.DataSheet4U.com
TSA1204
DUAL-CHANNEL, 12-BIT, 20MSPS, 120mW A/D CONVERTER
s 0.5Msps to 20Msps sampling frequency
s Adaptive power consumption: 120mW @
20Msps, 95mW@10Msps
s Single supply voltage: 2.5V
Independent supply for CMOS output stage
with 2.5V/3.3V capability
s ENOB=11.2 @ Nyquist
s SFDR= -81.5 dBc @ Nyquist
s 1GHz analog bandwidth Track-and-Hold
s Common clocking between channels
s Dual simultaneous Sample and Hold inputs
s Multiplexed outputs
s Built-in reference voltage with external bias
capability.
DESCRIPTION
The TSA1204 is a new generation of high speed,
dual-channel Analog to Digital converter pro-
cessed in a mainstream 0.25µm CMOS technolo-
gy yielding high performances and very low power
consumption.
The TSA1204 is specifically designed for applica-
tions requiring very low noise floor, high SFDR
and good isolation between channels. It is based
on a pipeline structure and digital error correction
to provide excellent static linearity and over 11.2
effective bits at Fs=20Msps, and Fin=10MHz.
For each channel, a voltage reference is integrat-
ed to simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with external references.
Each ADC outputs are multiplexed in a common
bus with small number of pins. A tri-state capabili-
ty is available for the outputs, allowing chip selec-
tion. The inputs of the ADC must be differentially
driven.
The TSA1204 is available in extended (-40 to
+85°C) temperature range, in a small 48 pins
TQFP package.
APPLICATIONS
s Medical imaging and ultrasound
s 3G base station
s I/Q signal processing applications
s High speed data acquisition system
s Portable instrumentation
ORDER CODE
Part Number
Temperature
Range
TSA1204IF
TSA1204IFT
EVAL1204/BA
-40°C to +85°C
-40°C to +85°C
February 2003
Package Conditioning Marking
TQFP48
Tray
TQFP48 Tape & Reel
Evaluation board
SA1204I
SA1204I
PIN CONNECTIONS (top view)
index
corner
AGND 1
INI 2
AGND 3
INIB 4
AGND 5
IPOL 6
AVCCB 7
AGND 8
INQ 9
AGND 10
INBQ 11
AGND 12
48 47 46 45 44 43 42 41 40 39 38 37
36 D2
35 D3
34 D4
33 D5
32 D6
TSA1204
31 D7
30 D8
29 D9
28 D10
27 D11(MSB)
26 VCCBE
25 GNDBE
13 14 15 16 17 18 19 20 21 22 23 24
BLOCK DIAGRAM
+2.5V/3.3V
CLK SELECT OEB VCCBE
VINI
VINBI
VINCMI
VREFPI
VREFMI
IPOL
VREFPQ
VREFMQ
VINCMQ
VINQ
VINBQ
AD 12
I channel
common mode
REF I
Polar.
REF Q
common mode
AD 12
Q channel
Timing
12
M 12
12 D0
U Buffers
TO
X D11
12
GND
GNDBE
PACKAGE
7 × 7 mm TQFP48
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TSA1204 pdf, 반도체, 판매, 대치품
TSA1204
PIN DESCRIPTION
Pin No Name
Description
Observation
1 AGND Analog ground
0V
2 INI I channel analog input
3 AGND Analog ground
0V
4 INBI I channel inverted analog input
5 AGND Analog ground
0V
6 IPOL Analog bias current input
7 AVCC Analog power supply
2.5V
8 AGND Analog ground
0V
9 INQ Q channel analog input
10 AGND Analog ground
0V
11 INBQ Q channel inverted analog input
12 AGND Analog ground
0V
13 REFPQ Q channel top reference voltage
14 REFMQ Q channel bottom reference
voltage
0V
15 INCMQ Q channel input common mode
16 AGND Analog ground
17 AVCC Analog power supply
18 DVCC Digital power supply
19 DGND Digital ground
20 CLK Clock input
21 SELECT Channel selection
22 DGND Digital ground
23 DVCC Digital power supply
24 GNDBI Digital buffer ground
0V
2.5V
2.5V
0V
2.5V CMOS input
2.5V CMOS input
0V
2.5V
0V
Pin No Name
Description
25 GNDBE Digital buffer ground
26 VCCBE Digital Buffer power supply
27 D11(MSB) Most Significant Bit output
28 D10 Digital output
29 D9 Digital output
30 D8 Digital output
31 D7 Digital output
32 D6 Digital output
33 D5 Digital output
34 D4 Digital output
35 D3 Digital output
36 D2 Digital output
37 D1 Digital output
38 D0(LSB) Least Significant Bit output
Observation
0V
2.5V/3.3V
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
39 VCCBE Digital Buffer power supply
2.5V/3.3V - See Application
Note
40 GNDBE Digital buffer ground
0V
41 VCCBI Digital Buffer power supply
2.5V
42 DVCC Digital Buffer power supply
2.5V
43 OEB Output Enable input
2.5V/3.3V CMOS input
44 AVCC Analog power supply
2.5V
45 AVCC Analog power supply
2.5V
46 INCMI I channel input common mode
47 REFMI I channel bottom reference voltage 0V
48 REFPI I channel top reference voltage
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Values
Unit
AVCC Analog Supply voltage 1)
0 to 3.3
V
DVCC Digital Supply voltage 1)
0 to 3.3
V
VCCBE Digital buffer Supply voltage 1)
0 to 3.6
V
VCCBI Digital buffer Supply voltage 1)
0 to 3.3
V
IDout Digital output current
-100 to 100
mA
Tstg Storage temperature
+150
°C
ESD
HBM: Human Body Model2)
CDM: Charged Device Model3)
2
kV
1.5
Latch-up Class4)
A
1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC
2). ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5k
3). Discharge to Ground of a device that has been previously charged.
4). Corporate ST Microelectronics procedure number 0018695
OPERATING CONDITIONS
Symbol
AVCC
DVCC
VCCBE
VCCBI
Parameter
Analog Supply voltage
Digital Supply voltage
External Digital buffer Supply voltage
Internal Digital buffer Supply voltage
Min
Typ
Max
Unit
2.25
2.5
2.25
2.5
1.8 2.5
2.25
2.5
2.7
2.7
3.5
2.7
V
V
V
V
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TSA1204 전자부품, 판매, 대치품
DEFINITIONS OF SPECIFIED PARAMETERS
STATIC PARAMETERS
Static measurements are performed through
method of histograms on a 2MHz input signal,
sampled at 20Msps, which is high enough to fully
characterize the test frequency response. The
input level is +1dBFS to saturate the signal.
Differential Non Linearity (DNL)
The average deviation of any output code width
from the ideal code width of 1 LSB.
Integral Non linearity (INL)
An ideal converter presents a transfer function as
being the straight line from the starting code to the
ending code. The INL is the deviation for each
transition from this ideal curve.
DYNAMIC PARAMETERS
Dynamic measurements are performed by
spectral analysis, applied to an input sine wave of
various frequencies and sampled at 20Msps.
The input level is -1dBFS to measure the linear
behavior of the converter. All the parameters are
given without correction for the full scale ampli-
tude performance except the calculated ENOB
parameter.
Spurious Free Dynamic Range (SFDR)
The ratio between the power of the worst spurious
signal (not always an harmonic) and the amplitude
of fundamental tone (signal power) over the full
Nyquist band. It is expressed in dBc.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first five harmonic
distortion components to the rms value of the
fundamental line. It is expressed in dB.
TSA1204
Signal to Noise Ratio (SNR)
The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
components in the Nyquist band (fs/2) excluding
DC, fundamental and the first five harmonics.
SNR is reported in dB.
Signal to Noise and Distortion Ratio (SINAD)
Similar ratio as for SNR but including the harmonic
distortion components in the noise figure (not DC
signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits
(ENOB) can easily be deduced using the formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but
has an A0 amplitude, the SINAD expression
becomes:
SINAD2Ao=SINADFull Scale+ 20 log (2A0/FS)
SINAD2Ao=6.02 × ENOB + 1.76 dB + 20 log (2A0/
FS)
The ENOB is expressed in bits.
Analog Input Bandwidth
The maximum analog input frequency at which the
spectral response of a full power signal is reduced
by 3dB. Higher values can be achieved with
smaller input levels.
Effective Resolution Bandwidth (ERB)
The band of input signal frequencies that the ADC
is intended to convert without loosing linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.
Pipeline delay
Delay between the initial sample of the analog
input and the availability of the corresponding
digital data output, on the output bus. Also called
data latency. It is expressed as a number of clock
cycles.
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