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부품번호 | 74LVX573 기능 |
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기능 | LOW VOLTAGE CMOS OCTAL D-TYPE LATCH | ||
제조업체 | ST Microelectronics | ||
로고 | |||
전체 10 페이지수
www.DataSheet4U.com
74LVX573
LOW VOLTAGE CMOS OCTAL D-TYPE LATCH
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
s HIGH SPEED:
tPD=6.4ns (TYP.) at VCC = 3.3V
s 5V TOLERANT INPUTS
s POWER-DOWN PROTECTION ON INPUTS
s INPUT VOLTAGE LEVEL:
VIL = 0.8V, VIH = 2V at VCC =3V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s LOW NOISE:
VOLP = 0.3V (TYP.) at VCC =3.3V
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4 mA (MIN) at VCC = 3V
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
PIN CONNECTION AND IEC LOGIC SYMBOLS
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVX573M
T&R
74LVX573MTR
74LVX573TTR
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2001
1/10
74LVX573
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
VOLP
VOLV
Dynamic Low
Voltage Quiet
Output (note 1, 2)
3.3
0.3
-0.8 -0.3
0.8
VIHD
Dynamic High
Voltage Input
(note 1, 3)
3.3 CL = 50 pF 2.0
V
VILD
Dynamic Low
Voltage Input
(note 1, 3)
3.3
0.8
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
Test Condition
Value
Symbol
Parameter
VCC CL
(V) (pF)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
tPLH Propagation Delay 2.7 15
tPHL
Time
LE to Q
2.7 50
3.3(*) 15
8.2 15.6 1.0 18.5 1.0 18.5
10.7 19.1 1.0 22.0 1.0 22.0
ns
6.4 10.1 1.0 12.0 1.0 12.0
3.3(*) 50
8.9 13.6 1.0 15.5 1.0 15.5
tPLH Propagation Delay 2.7 15
tPHL Time
D to Q
2.7 50
3.3(*) 15
7.6 14.5 1.0 17.5 1.0 17.5
10.1 18.0 1.0 21.0 1.0 21.0
ns
5.9 9.3 1.0 11.0 1.0 11.0
3.3(*) 50
8.4 12.8 1.0 14.5 1.0 14.5
tPZL
tPZH
Output Enable
Time
2.7
2.7
3.3(*)
15
50
15
7.8 15.0 1.0 18.5 1.0 18.5
10.3 18.5 1.0 22.0 1.0 22.0
6.1 9.7 1.0 12.0 1.0 12.0 ns
3.3(*) 50
8.6 13.2 1.0 15.5 1.0 15.5
tPLZ
tPHZ
Output Disable
Time
2.7 50
3.3(*) 50
12.1 19.1 1.0 22.0 1.0 22.0
ns
10.1 13.6 1.0 15.5 1.0 15.5
tW
LE pulse Width,
HIGH
2.7 50
3.3(*) 50
6.5 7.5 7.5
ns
5.0 5.0 5.0
tS
Setup Time D to LE 2.7 50
HIGH or LOW
3.3(*) 50
5.0 5.0 5.0
ns
3.5 3.5 3.5
th
Hold Time D to LE 2.7 50
HIGH or LOW
3.3(*) 50
1.5 1.5 1.5
ns
1.5 1.5 1.5
tOSLH
tOSHL
Output to Output
Skew Time (note
1,2)
2.7 50
3.3(*) 50
0.5 1.0 1.5 1.5
ns
0.5 1.0 1.5 1.5
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
4/10
4페이지 WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
74LVX573
7/10
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
74LVX573 | Low Voltage Octal Latch with 3-STATE Outputs | Fairchild Semiconductor |
74LVX573 | LOW VOLTAGE CMOS OCTAL D-TYPE LATCH | ST Microelectronics |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |