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PDF K4Y50024UC Data sheet ( Hoja de datos )
| Número de pieza | K4Y50024UC | |
| Descripción | (K4Y50024UC - K4Y50164UC) 512Mbit XDR TM DRAM | |
| Fabricantes | Samsung semiconductor | |
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K4Y50164UC
K4Y50084UC
K4Y50044UC
K4Y50024UC
www.DataSheet4U.com
XDRTM DRAM
512Mbit XDRTM DRAM(C-die)
Revision 1.1
August 2006
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
XDR is a trademark of Rambus Inc.
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XDRTM DRAM
3.0 General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets of pins used for normal
memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins. The “N” appended to a
signal name denotes the complementary signal of a differential pair.
A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on the signals of a bus.
There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus uses a set of 2 bit-windows on each signal,
while the DQ bus uses a set of 16 bit-windows on each signal.
In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T0 contains an activate (ACT) command. This
causes row Ra of bank Ba in the memory component to be loaded into the sense amp array for the bank. A second request packet at
clock edge T1 contains a write (WR) command. This causes the data packet D(a1) at edge T4 to be written to column Ca1 of the sense
amp array for bank Ba. A third request packet at clock edge T3 contains another write (WR) command. This causes the data packet
D(a2) at edge T6 to also be written to column Ca2. A final request packet at clock edge T13 contains a precharge (PRE) command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-W , tCC , and tWRP . In
addition, the spacing between the request packets and data packets is constrained by the tCWD parameter. The spacing of the CFM/
CFMN clock edges is constrained by tCYCLE.
Figure 1 : XDR DRAM Device Write and Read Transactions
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CFM
CFMN
RQ11..0
ACT WR
a0 a1
WR
a2
DQ15..0tRCD-W
DQN15..0
tCC
tCWD
D(a1)
tWRP
D(a2)
PRE
a3
tCYCLE
Transaction a: WR a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Write Transaction
CFM
CFMN
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
RQ11..0
ACT
a0
DQ15..0
DQN15..0
tRCD-R
RD
a1
tCC
RD
a2 tRDP
tCAC
PRE
a3
Q(a1)
Q(a2)
tCYCLE
Transaction a: RD a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Read Transaction
The read transaction shows a request packet at clock edge T0 containing an ACT command. This causes row Ra of bank Ba of the mem-
ory component to load into the sense amp array for the bank. A second request packet at clock edge T5 contains a read (RD) command.
This causes the data packet Q(a1) at edge T11 to be read from column Ca1 of the sense amp array for bank Ba. A third request packet
at clock edge T7 contains another RD command. This causes the data packet Q(a2) at edge T13 to also be read from column Ca2. A final
request packet at clock edge T10 contains a PRE command.
The spacings between the request packets are constrained by the following timing parameters in the diagram: tRCD-R , tCC , and tRDP . In
addition, the spacing between the request and data packets are constrained by the tCAC parameter.
* Any system or application incorporating random access memory products should be properly designed, tested and qualified to ensure
proper use or access of such memory products. Disproportionate, excessive and/or repeated access to a particular address or
addresses may result in reduction of product life.
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XDRTM DRAM
6.0 Block Diagram
A block diagram of the XDR DRAM device is shown in Figure2. It shows all interface pins and major internal blocks.
The CFM and CFMN clock signals are received and used by the clock generation logic to produce three virtual clock signals : 1/tCYCLE,
2/tCYCLE, and 16/tCC. The frequency of these signals are 1x, 2x, and 8x that of the CFM and CFMN signals. These virtual signals show
the effective data rate of the logic blocks to which they connect; they are not necessarily present in the actual memory component.
The RQ11 ... RQ0 pins receive the request packet. Two 12-bit words are received in one tCYCLE interval. This is indicated by the 2/tCYCLE
clocking signal connected to the 1:2 Demux Block that assembles the 24-bit request packet. These 24bits are loaded into a regis-
ter(clocked by the 1/tCYCLE clocking signal) and decoded by the Decode Block. The VREF pin supplies a reference voltage used by the
RQ receivers.
Three sets of control signals are produced by the Decode Block. These include the bank(BA) and row(R) addresses for an activate(ACT)
command, the bank(BR) and row(REFr) addresses for a refresh activate(REFA) command, the bank(BP) address for a precharge(PRE)
command, the bank(BR) adddress for a refresh precharge(REFP) command, and the bank(BC) and column(C and SC) addresses for a
read(RD) or write(WR or WRM) command. In addition, a mask(M) is used for a masked write(WRM) command.
These commands can all be optionally delayed in increments of tCYCLE under control of delay fields in the request. The control signals of
the commands are loaded into registers and presented to the memory core. These registers are clocked at maximum rates determined
by core timing parameters, in this case 1/tRR, 1/tPP, and 1/tCC(1/4, 1/4, and 1/2 the frequency of CFM in the -3200 component). These
registers may be loaded at any tCYCLE rising edge. Once loaded, they should not be changed until a tRR, tPP, or tCC time later because
timing paths of the memory core need time to settle.
A bank address is decoded for an ACT command. The indicated row of the selected bank is sensed and placed into the associated sense
amp array for the bank. Sensing a row is also referred to as “Opening a page”for the bank.
Another bank address is decoded for a PRE command. The indicated bank and associated sense amp array are precharged to a state in
which a subsequent ACT command can be applied. Precharging a bank is also called “closing the page” for the bank.
After a bank is given an ACT command and before it is given a PRE command, it may receive read(RD) and write(WR) column commands.
These commands permit the data in the bank’s associated sense amp array to be accessed.
For a WR command, the bank address is decoded. The indicated column of the associated sense amp array of the selected bank is written
with the data received from the DQ15 ... DQ0 pins.
The bank address is decoded for a RD command. The indicated column of the selected bank’s associated sense amp array is read. The
data is transmitted onto the DQ15 ... DQ0 pins.
The DQ15 ... DQ0 pins receive the write data packet(D) for a write transaction. 16 sixteen-bit words are received in one tCC interval. This
is indicated by the 16/tCC clocking signal connected to the 1:16 Demux Block that assembles the 16x16-bit write data packet. The write
data is then driven to the selected Sense Amp Array Bank.
16 sixteen-bit words are accessed in the selected Sense Amp Array Bank for a read transaction. The DQ15 ... DQ0 pins transmit the read
data packet(Q) in one tCC interval. This is indicated by the 16/tCC clocking signal connected to the 16:1 Mux Block. The VTERM pin supplies
a termination voltage for the DQ pins.
The RST, SCK, and CMD pins connect to the Control Register block. These pins supply the data, address and conrol needed to write the
control registers. The read data for these registers is accessed through the SDO/SDI pins. These pins are also used to initialize the device.
The control registers are used to transition between power modes, and are also used for calibrating the high speed transmit and receive
circuits of the device. The control registers also supply bank(REFB) and row(REFr) address for refresh operations.
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