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부품번호 | A49LF040 기능 |
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기능 | 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory | ||
제조업체 | AMIC Technology | ||
로고 | |||
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Preliminary
A49LF040
4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
Document Title
4 Mbit CMOS 3.3 Volt-only Low Pin Count Flash Memory
Revision History
Rev. No.
0.0
0.1
History
Initial issue
Add Pb-Free package type
Issue Date
February 17, 2004
August 20, 2004
Remark
Preliminary
PRELIMINARY (August, 2004, Version 0.1)
AMIC Technology, Corp.
BLOCK DIAGRAM
TBL# WP# INIT#
LAD[3:0]
LCLK
LFRAME#
ID[3:0]
GPI[4:0]
A[10:0]
I/O7 ~ I/O0
WE#
OE#
R/C#
MODE
RST#
RB#
LPC Mode
Interface
A/A Mux
Mode
Interface
A49LF040
Control Logic
Input/Output
Buffers
High Voltage
Generator
Data Latch
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
PRELIMINARY (August, 2004, Version 0.1)
3
AMIC Technology, Corp.
4페이지 A49LF040
Table 2: LPC Read Cycle
Clock
Cycle
Field
Name
Field Contents LAD[3:0]
LAD[3:0]1
Direction
Comments
1 START
2
CYCTYPE
+ DIR
3-10 ADDRESS
0000
010X
YYYY
11 TAR0
1111
12 TAR1 1111(float)
13 SYNC
14 DATA
15 DATA
16 TAR0
0000
ZZZZ
ZZZZ
1111
17 TAR1 1111(float)
IN
IN
IN
IN
then Float
Float
then OUT
OUT
OUT
OUT
IN
then Float
Float
then OUT
LFRAME# must be active (low) for the part to respond. Only the last
start field (before LFRAME# transitioning high) should be recognized.
Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle.
Bit 1 indicates the type of transfer “0” for Read. Bit 0 is reserved.
Address Phase for Memory Cycle. LPC protocol supports a 32-bit
address phase. YYYY is one nibble of the entire address. Addresses
are transferred most-significant nibble first. See Table 4 for address
bits definition and Table 5 for valid memory address range.
In this clock cycle, the host has driven the bus to all 1s and then floats
the bus. This is the first part of the bus “turnaround cycle.”
The A49LF040 takes control of the bus during this cycle.
The A49LF040 outputs the value 0000b indicating that data will be
available during the next clock cycle.
This field is the least-significant nibble of the data byte.
This field is the most-significant nibble of the data byte.
In this clock, the host has driven the bus to all 1s and then floats the
bus. This is the first part of the bus “turnaround cycle.”
The A49LF040 takes control of the bus during this cycle.
1. Field contents are valid on the rising edge of the present clock cycle.
LPC Single-Byte Read Waveforms
LCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
LFRAME#
LAD[3:0]
START
CYCTYPE +
DIR
ADDRESS
TAR0 TAR1 SYNC
DATA
TAR0 TAR1
PRELIMINARY (August, 2004, Version 0.1)
6
AMIC Technology, Corp.
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부품번호 | 상세설명 및 기능 | 제조사 |
A49LF040 | 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory | AMIC Technology |
A49LF040A | 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory | AMIC Technology |
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