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PDF 54LVX3245 Data sheet ( Hoja de datos )
| Número de pieza | 54LVX3245 | |
| Descripción | 8-Bit Dual Supply Translating Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
January 1999
54LVX3245
8-Bit Dual Supply Translating Transceiver with
TRI-STATE® Outputs
General Description
The LVX3245 is a dual-supply, 8-bit translating transceiver
that is designed to interface between a 3V bus and a 5V bus
in a mixed 3V/5V supply environment. The Transmit/Receive
(T/R) input determines the direction of data flow. Transmit
(active-HIGH) enables data from A ports to B ports; Receive
(active-LOW) enables data from B ports to A ports. The Out-
put Enable input, when HIGH, disables both A and B ports by
placing them in a TRI-STATE condition. The A port interfaces
with the 3V bus; the B port interfaces with the 5V bus.
The LVX3245 is suitable for mixed voltage applications such
as systems using 3.3V memories which must interface with
existing busses or other components operating at 5.0V.
Features
n Bidirectional interface between 3V and 5V buses
n Inputs compatible with TTL level
n 3V data flow at A port and 5V data flow at B port
n Outputs source/sink 24 mA
n Available in ceramic DIP and Flatpack packages
n Implements proprietary EMI reduction circuitry
n Functionally compatible with the 54 series 245
n Standard Microcircuit Drawing (SMD) 5962-9860501
Ordering Code
Order Number
54LVX3245J-QML
54LVX3245W-QML
Package Number
J24F
W24C
Package Description
24-Lead Ceramic Dual-in-line
24-Lead Cerpack
Logic Symbol
Connection Diagram
Pin Assignment
for CDIP and Cerpack
DS101018-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS101018
DS101018-2
www.national.com
1 page  
AC Electrical Characteristics
Symbol
Parameters
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPZL
tPZH
tPHZ
tPLZ
tPHZ
tPLZ
tOSHL
tOSLH
Propagation
Delay
A to B
Propagation
Delay
B to A
Output Enable
Time OE to B
Output Enable
Time OE to A
Output Disable
Time OE to B
Output Disable
Time OE to A
Output to Output
Skew (Note 8)
Data to Output
TA = −55˚C to +125˚C
CL = 50 pF
VCCA = 3.3V (Note 7)
VCCB = 5.0V (Note 6)
Min Max
1.0 8.5
1.0 8.5
1.0 8.0
1.0 8.0
1.0 8.5
1.0 8.5
1.0 9.5
1.0 9.5
1.0 7.5
1.0 7.5
1.0 7.0
1.0 7.0
1.5
TA = −55˚C to +125˚C
CL = 50 pF
VCCA=2.7V
VCCB=5.0V (Note 6)
Min Max
1.0 9.0
1.0 9.0
1.0 8.5
1.0 8.5
1.0 9.0
1.0 9.0
1.0 10.5
1.0 10.5
1.0 7.5
1.0 7.5
1.0 7.0
1.0 7.0
1.5
Units
ns
ns
ns
ns
ns
ns
ns
Note 6: Voltage Range 5.0V is 5.0V ±0.5V.
Note 7: Voltage Range 3.3V is 3.3V ±0.3V.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
CIN
CI/O
CPD
Parameter
Input Capacitance
Input/Output
Capacitance
Power Dissipation
Capacitance
Note 9: CPD is measured at 10 MHz
Max
10
12
50
8-Bit Dual Supply Translating Transceiver
The LVX3245 is a dual supply device capable of bidirectional
signal translation. This level shifting ability provides an effi-
cient interface between low voltage CPU local bus with
memory and a standard bus defined by 5V I/O levels. The
device control inputs can be controlled by either the low volt-
age CPU and core logic or a bus arbitrator with 5V I/O levels.
Manufactured on a sub-micron CMOS process, the LVX3245
is suitable for mixed voltage applications such as systems
using 3.3V memories which must interface with existing bus-
ses or other components operating at 5.0V.
Units
pF
pF
pF
Conditions
VCC = Open
VCCA = 3.3V
VCCB = 5.0V
VCCB = 5.0V
VCCA = 3.3V
DS101018-3
5 www.national.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 54LVX3245.PDF ] | |
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