AD7952 Datasheet PDF - Analog Devices
| Part Number | AD7952 | |
| Description | Programmable Input PulSAR ADC | |
| Manufacturers | Analog Devices | |
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14-Bit, 1 MSPS, Differential,
Programmable Input PulSAR® ADC
AD7952
FEATURES
Multiple pins/software-programmable input ranges
+5 V (10 V p-p), +10 V (20 V p-p), ±5 V (20 V p-p),
±10 V (40 V p-p)
Pins or serial SPI®-compatible input ranges/mode selection
Throughput
1 MSPS (warp mode)
800 kSPS (normal mode)
670 kSPS (impulse mode)
14-bit resolution with no missing codes
INL: ±0.3 LSB typical, ±1 LSB maximum (±61 ppm of FSR)
SNR: 85 dB @ 2 kHz
iCMOS® process technology
5 V internal reference: typical drift 3 ppm/°C; TEMP output
No pipeline delay (SAR architecture)
Parallel (14- or 8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation
235 mW @ 1 MSPS
10 mW @ 1 kSPS
48-lead LQFP and 48-lead LFCSP (7 mm × 7 mm)
APPLICATIONS
Process controls
Medical instruments
High speed data acquisition
Digital signal processing
Instrumentation
Spectrum analysis
ATE
GENERAL DESCRIPTION
The AD7952 is a 14-bit, charge redistribution, successive
approximation register (SAR) architecture analog-to-digital
converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS
high voltage process. The device is configured through hardware or
via a dedicated write-only serial configuration port for input
range and operating mode. The AD7952 contains a high speed
14-bit sampling ADC, an internal conversion clock, an internal
reference (and buffer), error correction circuits, and both serial
and parallel system interface ports. A falling edge on CNVST
samples the fully differential analog inputs on IN+ and IN−.
The AD7952 features four different analog input ranges and three
different sampling modes: warp mode for the fastest throughput,
normal mode for the fastest asynchronous throughput, and
impulse mode where power is scaled with throughput.
Operation is specified from −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND
AGND
AVDD
PDREF
PDBUF
IN+
IN–
REF
AMP
REF
SWITCHED
CAP DAC
CNVST
PD
RESET
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
AD7952
SERIAL DATA
PORT
SERIAL
CONFIGURATION
PORT
14
PARALLEL
INTERFACE
OVDD
OGND
D[13:0]
SER/PAR
BYTESWAP
OB/2C
BUSY
RD
CS
WARP IMPULSE BIPOLAR TEN
Figure 1.
Table 1. 48-Lead PulSAR Selection
Input Type
100 to
Res 250
(Bits) (kSPS)
500 to
570
(kSPS)
Bipolar
14
Differential
Bipolar
14
Unipolar
16 AD7651
AD7660 AD7650
AD7661 AD7652
AD7664
AD7666
Bipolar
16 AD7610 AD7665
AD7663
Differential 16 AD7675 AD7676
Unipolar
Simultaneous/
Multichannel
Unipolar
Differential
Unipolar
Differential
Bipolar
16
18
18
AD7654
AD7655
AD7678 AD7679
AD7631
570 to
1000
(kSPS)
AD7951
AD7952
>1000
kSPS
AD7653
AD7667
AD7612
AD7671
AD7677
AD7621
AD7622
AD7623
AD7674
AD7634
AD7641
AD7643
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
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AD7952
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (See Figure 34 and Figure 35)
Convert Pulse Width
Time Between Conversions
Warp Mode/Normal Mode/Impulse Mode1
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Warp Mode/Normal Mode/Impulse Mode
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Warp Mode/Normal Mode/Impulse Mode
Acquisition Time
Warp Mode/Normal Mode/Impulse Mode
RESET Pulse Width
PARALLEL INTERFACE MODES (See Figure 36 and Figure 38)
CNVST Low to DATA Valid Delay
Warp Mode/Normal Mode/Impulse Mode
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES2 (See Figure 40 and Figure 41)
CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay2
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Asserted to SDCLK First Edge Delay
Internal SDCLK Period3
Internal SDCLK High3
Internal SDCLK Low3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SDCLK Last Edge to SYNC Delay3
CS High to SYNC High-Z
CS High to Internal SDCLK High-Z
CS High to SDOUT High-Z
BUSY High in Master Serial Read After Convert3
CNVST Low to SYNC Delay, Read After Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Deasserted to BUSY Low Delay
Symbol Min
Typ
Max
Unit
t1 10
t2
1/1.25/1.49
t3
t4
t5
t6 10
t7
2
t8
200
t9 10
ns
μs
35 ns
850/1100/1350
ns
ns
ns
850/1100/1350 ns
ns
ns
t10
t11 20
t12
t13 2
850/1100/1350
40
15
ns
ns
ns
ns
t14
t15
t16
t17
t18 3
t19 30
t20 15
t21 10
t22 4
t23 5
t24 5
t25
t26
t27
t28
t29
t30
50/290/530
10
10
10
45
See Table 4
10
10
10
710/950/1190
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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