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부품번호 | STE10A 기능 |
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기능 | PCI 10/100 Ethernet controller | ||
제조업체 | ST Microelectronics | ||
로고 | |||
전체 70 페이지수
www.DataSheet4U.com
STE10/100A
PCI 10/100 Ethernet controller with integrated PHY (3.3V)
Features
■ IEEE802.3u 100BASE-TX and IEEE802.3
10BASE-T compliant
■ Support for IEEE802.3x flow control
■ IEEE802.3u auto-negotiation support for
10BASE-T and 100BASE-TX
■ PCI bus interface rev. 2.2 compliant
■ ACPI and PCI power management standard
compliant
■ Support for PC99 wake on LAN
■ Provides 32-bit PCI bus master data transfer at
PCI clocks of 20-33 MHz
■ Provides writable EEPROM/Boot rom interface
■ Provides independent transmission and
receiving FIFOs, each 2k bytes long
■ Supports big endian or little endian byte
ordering
■ ACPI and PCI compliant power management
functions offer significant power-savings
performance
■ Provides general purpose timers
■ 128-pin QFP package
PQFP128 (14mm x 20mm x 2.7mm)
Description
The STE10/100A is a high performing PCI fast
ethernet controller with integrated physical layer
interface for 10BASE-T and 100BASE-TX
applications.
It was designed with advanced CMOS technology
to provide glueless 32-bit bus master interface for
PCI bus, boot ROM interface, CSMA/CD protocol
for fast ethernet, as well as the physical media
interface for 100BASE-TX of IEEE802.3u and
10BASE-T of IEEE802.3. The auto-negotiation
function is also supported for speed and duplex
detection.
The STE10/100A provides both half-duplex and
full-duplex operation, as well as support for full-
duplex flow control. It provides long FIFO buffers
for transmission and receiving, and early interrupt
mechanism to enhance performance. The
STE10/100A also supports ACPI and PCI
compliant power management function
February 2007
Rev 8
1/82
www.st.com
82
Overview
1 Overview
STE10/100A
1.1
Block diagrams
Figure 1. STE10/100A block diagram
Flow
control
DMA
Tx FiFo
Rx FiFo
EMI
Manchester
encoder
10 TX filter
4B/5B
Scrambler
Auto-negociation
5B/4B
Descrambler
100 clock
recovery
Manchester
decoder
Transmitter
25MHz
Base line
restore
125MHz
TX freq. synth.
20MHz
Adaptive
equalization
Link polarity
10 clock
recovery
PC00347
Figure 2. STE10/100A system diagram
Serial EEPROM
Boot ROM
PCI
interface
STE10/100A
Xfmr
Medium
LEDs
25MHz crystal
PC00348
4/82
4페이지 STE10/100A
2 Pin description
Figure 3. Pin connection
Pin description
7/82
7페이지 | |||
구 성 | 총 70 페이지수 | ||
다운로드 | [ STE10A.PDF 데이터시트 ] |
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