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부품번호 A3985 기능
기능 Digitally Programmable Dual Full-Bridge MOSFET Driver
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A3985 데이터시트, 핀배열, 회로
www.DataSheet4U.com
A3985
Digitally Programmable
Dual Full-Bridge MOSFET Driver
Features and Benefits
Serial interface for full digital control
Dual full-bridge gate drive for N-channel MOSFETs
Dual 6-bit DAC current reference
Operation over 12 to 50 V supply voltage range
Synchronous rectification
Cross-conduction protection
Adjustable mixed decay
Fixed off-time PWM current control
Low-current idle mode
Package: 38 pin TSSOP (suffix LD)
Description
The A3985 is a flexible dual full-bridge gate driver suitable
for driving a wide range of higher power industrial bipolar 2-
phase stepper motors or 2-phase brushless dc motors. It can
also be used to drive two individual torque motors or solenoid
actuators. Motor power is provided by external N-channel power
MOSFETs at supply voltages from 12 to 50 V.
Full digital control is provided by two serially-accessible
registers that allow programming of off-time, blank-time,
dead-time, mixed decay ratios, synchronous rectification,
master clock source selection, and division ratio and idle
mode. All internal timings are derived from a master clock
that can be generated on-chip or provided by an external
clock such as the system clock of the master controller. A
programmable divider allows for a wide range of external
system clock frequencies.
The internal fixed off-time PWM current-control timing is
programmed via the serial interface to operate in slow, fast,
and mixed current-decay modes. The desired load-current level
and direction is set via the serial port with a direction bit and
two 6-bit linear DACs in conjunction with a reference voltage.
The seven bits of control allow maximum flexibility in torque
Approximate size
Continued on the next page…
Typical Application
3985-DS




A3985 pdf, 반도체, 판매, 대치품
A3985
Digitally Programmable
Dual Full-Bridge MOSFET Driver
ELECTRICAL CHARACTERISTICS at TA = 25°C, VDD = 5 V, VBB = 12 to 50 V, unless noted otherwise
Characteristics
Symbol
Test Conditions
Min. Typ.
Supply and Reference
Load Supply Voltage Range
Load Supply Current
Load Supply Idle Current
Logic Supply Voltage Range
Logic Supply Current
Logic Supply Idle Current
Regulator Output
Bootstrap Diode Forward Voltage
Gate Output Drive
Turn-On Rise Time
Turn-Off Fall Time
Turn-On Propagation Delay
Turn-Off Propagation Delay
Crossover Dead Time
VBB
IBB
IBBQ
VDD
IDD
IDDQ
VREG
VfBOOT
fMCK = 4 MHz, CLOAD = 1000 pF
ENABLE = High, outputs disabled
Word1:Bit D18 = 0
Word1:Bit D18 = 0
IREGInt = 30 mA
IfBOOT = 10 mA
tr
tf
tp(on)
tp(off)
tDEAD
CLOAD = 1000 pF, 20% to 80%
CLOAD = 1000 pF, 80% to 20%
ENABLE low to gate drive on
ENABLE high to gate drive off
fMCK = 4 MHz,
Word1:Bits D1 and D2 = 00
12
3.0
11.25
0.6
80
40
0.5
0.8
120
60
120
120
Pull-Up On Resistance
Pull-Down On Resistance
Short-Circuit Current – Source1
Short-Circuit Current – Sink
GHx Output Voltage
GLx Output Voltage
RDS(on)UP
RDS(on)DN
ISC(source)
ISC(sink)
VGHx
IGH = –25 mA
IGL = 25 mA
CBOOTx fully charged
VGLx
30
14
–140
160
VC – 0.2
VREG
0.2
40
19
–110
200
Logic Inputs
Input Low Voltage
Input High Voltage
Input Hysteresis
Input Current1
Output Low Voltage
VIL
VIH
VIHys
IIN
VOL
SDO, IOL= 0.5 mA
0.7 VDD
150
–1
300
Output High Voltage
VOH SDO, IOH= –0.3 mA
VDD
0.5
Output Leakage current1
IOleak SDO, STR = 1, 0 V< VO< VDD
–1
Max. Units
50 V
10 mA
6 mA
100 μA
5.5 V
10 mA
300 μA
13 V
1V
160 ns
80 ns
– ns
– ns
0.75 μs
55 Ω
24 Ω
–80 mA
250 mA
–V
–V
0.3 VDD
1
0.5
V
V
mV
μA
V
V
1 μA
Continued on the next page...
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

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A3985 전자부품, 판매, 대치품
A3985
Digitally Programmable
Dual Full-Bridge MOSFET Driver
Functional Description
Basic Operation
The A3985 is a highly-configurable dual full-bridge FET
driver with built-in digital current control. All features are
accessed through a simple SPI (Serial Peripheral Interface)
compatible serial port, allowing multiple motors to be con-
trolled with as few as three wires.
Because the full-bridge control circuits are independently
controlled, the A3985 can be used to drive 2-phase bipolar
stepper motors and 2-phase brushless dc (BLDC) motors.
The current in each of the two external power full-bridges
(which are all N-channel MOSFETs) is regulated by a fixed
off-time PWM control circuit. The full-bridge current at each
step is set by the value of an external current sense resistor,
RSENSEX , in the ground connection to the bridge, a reference
voltage, VREF, and the output of the DAC controlled by the
serial data.
The use of PWM with N-channel MOSFETs provides the
most cost-effective solution for a high efficiency motor drive.
The A3985 provides all the necessary circuits to ensure
that the gate-source voltage of both high-side and low-side
external MOSFETs are above 10 V, and that there is no cross-
conduction (shoot through) in the external bridge. Specific
functions are described more fully in the following sections.
Power Supplies
Two power connections are required. The motor power sup-
ply should be connected to VBB to provide the gate drive
levels. Power for internal logic is provided by the VDD
input. Internal logic is designed to operate from 3 to 5.5 V,
allowing the use of 3.3 or 5 V external logic interface cir-
cuits.
GND The ground pin is a reference voltage for internal logic
and analog circuits. There is no large current flow through
this pin. To avoid any noise from switching circuits, this
should have an independent trace to the supply ground star
point.
VREG The voltage at this pin is generated by a low-drop-out
linear regulator from the VBB supply. It is used to oper-
ate the low-side gate drive outputs, GLxx, and to provide
the charging current for the bootstrap capacitors, CBOOTx.
To limit the voltage drop when the charge current is pro-
vided, this pin should be decoupled with a ceramic capaci-
tor, CREG, to ground. The value CREG should typically
be 40 times the value of the bootstrap capacitor for PWM
frequencies up to 14 kHz. Above 14 kHz, the minimum
recommended value can be determined from the following
formula:
CREG > CBOOT × 3 × fPWM ,
where CREG and CBOOT are in nF, and fPWM is the maximum
PWM frequency, in kHz. VREG is monitored, and if the volt-
age becomes too low, the outputs will be disabled.
REF The reference voltage, VREF, at this pin sets the
maximum (100%) peak current. The REF input is internally
limited to 2 V when a 20 kΩ pull-up resistor is connected
between VREF and VDD. This allows the maximum refer-
ence voltage to be set without the need for an externally-
generated voltage. An external reference voltage below the
maximum can also be input on this pin. The voltage at VREF
is divided by the range select ratio Gm to produce the DAC
reference voltage level.
OSC The PWM timing is based on a master clock, typically
running at 4 MHz. The master clock period is used to derive
the PWM off-time, dead time, and blanking time.
The master clock frequency can be set by an internal oscil-
lator or by one of three division ratios of an external clock.
These four options are selected by bits D12 and D13 of the
Control register word.
When the A3985 is configured to use an external clock,
this is input on the OSC pin and will usually provide more
precision than using the internal oscillator. The three internal
divider alternatives provide flexibility in setting the master
clock frequency based on available external system clocks.
If internal timing is selected, fOSC is configured by using
an external resistor, ROSC, connected from the OSC pin to
GND. This sets the frequency (in MHz) to approximately:
fOSC 100 / (6 + 1.9 × ROSC) ,
where ROSC, in kΩ, is typically between 50 kΩ and 10 kΩ.
Allegro MicroSystems, Inc.
7
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

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