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부품번호 ZL49021 기능
기능 (ZL49010 - ZL49031) Wide Dynamic Range DTMF Receiver
제조업체 Zarlink Semiconductor
로고 Zarlink Semiconductor 로고


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ZL49021 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ZL49010/1, ZL49020/1, ZL49030/1
Wide Dynamic Range DTMF Receiver
Data Sheet
Features
• Wide dynamic range (50dB) DTMF Receiver
• Call progress (CP) detection via cadence
indication
• 4-bit synchronous serial data output
• Software controlled guard time for ZL490x0
• Internal guard time circuitry for ZL490x1
• Powerdown option (ZL4901x & ZL4903x)
• 3.579MHz crystal or ceramic resonator (ZL4903x
and ZL4902x)
• External clock input (ZL4901x)
• Guarantees non-detection of spurious tones
Applications
• Integrated telephone answering machine
• End-to-end signalling
• Fax Machines
Description
The ZL490xx is a family of high performance DTMF
receivers which decode all 16 tone pairs into a 4-bit
binary code. These devices incorporate an AGC for
wide dynamic range and are suitable for end-to-end
signalling. The ZL490x0 provides an early steering
(ESt) logic output to indicate the detection of a DTMF
September 2003
Ordering Information
ZL49010DAA
ZL49011DAA
ZL49020DAA
ZL49021DAA
ZL49030DCA
ZL49030DCB
ZL49030DDA
ZL49030DDB
ZL49031DCA
ZL49031DCB
ZL49031DDA
ZL49031DDB
8 Pin PDIP Tubes
8 Pin PDIP Tubes
8 Pin PDIP Tubes
8 Pin PDIP Tubes
18 Pin SOIC Tubes
18 Pin SOIC Tape & Reel
20 Pin SSOP Tubes
20 Pin SSOP Tape & Reel
18 Pin SOIC Tubes
18 Pin SOIC Tape & Reel
20 Pin SSOP Tubes
20 Pin SSOP Tape & Reel
-40°C to +85°C
signal and requires external software guard time to
validate the DTMF digit. The ZL490x1, with preset
internal guard times, uses a delay steering (DStD)
logic output to indicate the detection of a valid DTMF
digit. The 4-bit DTMF binary digit can be clocked out
synchronously at the serial data (SD) output. The SD
pin is multiplexed with call progress detector output. In
the presence of supervisory tones, the call progress
1
PWDN
VDD
VSS
Voltage
Bias Circuit
AGC
Anti-
alias
Filter
Dial
Tone
Filter
2
OSC2
OSC1
(CLK)
Oscillator
and
Clock
Circuit
To All Chip Clocks
1. ZL49010/1 and ZL49030/1 only.
2. ZL49020/1 and ZL49030/1 only.
3. ZL490x1 only.
High
Group
Filter
Low
Group
Filter
Steering
Circuit
Digital
Detector
Algorithm
Code
Converter
and
Latch
Energy
Detection
Figure 1 - Functional Block Diagram
Digital
Guard
Time3
Parallel to
Serial
Converter
& Latch
Mux
ESt
or
DStD
ACK
SD
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.




ZL49021 pdf, 반도체, 판매, 대치품
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
output filters and squared by high gain limiting comparators. The resulting squarewave signals are applied to a
digital detection circuit where an averaging algorithm is employed to determine the valid DTMF signal. For
ZL490x0, upon recognition of a valid frequency from each tone group, the early steering (ESt) output will go high,
indicating that a DTMF tone has been detected. Any subsequent loss of DTMF signal condition will cause the ESt
pin to go low. For ZL490x1, an internal delayed steering counter validates the early steering signal after a
predetermined guard time which requires no external components. The delayed steering (DStD) will go high only
when the validation period has elapsed. Once the DStD output is high, the subsequent loss of early steering signal
due to DTMF signal dropout will activate the internal counter for a validation of tone absent guard time. The DStD
output will go low only after this validation period.
Energy Detection
The output signal from the AGC circuit is also applied to the energy detection circuit. The detection circuit consists
of a threshold comparator and an active integrator. When the signal level is above the threshold of the internal
comparator (-35dBm), the energy detector produces an energy present indication on the SD output. The integrator
ensure the SD output will remain at high even though the input signal is changing. When the input signal is
removed, the SD output will go low following the integrator decay time. Short decay time enables the signal
envelope (or cadence) to be generated at the SD output. An external microcontroller can monitor this output for
specific call progress signals. Since presence of speech and DTMF signals (above the threshold limit) can cause
the SD output to toggle, both ESt (DStD) and SD outputs should be monitored to ensure correct signal identification.
As the energy detector is multiplexed with the digital serial data output at the SD pin, the detector output is selected
at all times except during the time between the rising edge of the first pulse and the falling edge of the fourth pulse
applied at the ACK pin.
Serial Data (SD) Output
When a valid DTMF signal burst is present, ESt or DStD will go high. The application of four clock pulses on the
ACK pin will provide a 4-bit serial binary code representing the decoded DTMF digit on the SD pin output. The
rising edge of the first pulse applied on the ACK pin latches and shifts the least significant bit of the decoded digit
on the SD pin. The next three pulses on ACK pin will shift the remaining latched bits in a serial format (see Figure
5). If less than four pulses are applied to the ACK pin, new data cannot be latched even though ESt/DStD can be
valid. Clock pulses should be applied to clock out any remaining data bits to resume normal operation. Any
transitions in excess of four pulses will be ignored until the next rising edge of the ESt/DStD. ACK should idle at
logic low. The 4-bit binary representing all 16 standard DTMF digits are shown in Table .
Powerdown Mode (ZL4901x/4903x)
The ZL4901x/4903x devices offer a powerdown function to preserve power consumption when the device is not in
use. A logic high can be applied at the PWDN pin to place the device in powerdown mode. The ACK pin should be
kept at logic low to avoid undefined ESt/DStD and SD outputs (see Table 3).
FLOW
697
697
697
770
770
770
852
852
852
FHIGH
1209
1336
1477
1209
1336
1477
1209
1336
1477
DIGIT
1
2
3
4
5
6
7
8
9
b3
0
0
0
0
0
0
0
1
1
b2
0
0
0
1
1
1
1
0
0
Table 2 - Serial Decode Bit Table
b1
0
1
1
0
0
1
1
0
0
b0
1
0
1
0
1
0
1
0
1
4
Zarlink Semiconductor Inc.

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ZL49021 전자부품, 판매, 대치품
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
Absolute Maximum Ratings- Voltages are with respect to VSS=0V unless otherwise stated.
Parameter
Symbol
Min
Max
1 DC Power Supply Voltage
VDD-VSS
6
2 Voltage on any pin (other than supply)
VI/O -0.3 6.3
3 Current at any pin (other than supply)
II/O
10
4 Storage temperature
TS -65 150
5 Package power dissipation
PD 500
† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Units
V
V
mA
°C
mW
Recommended Operating Conditions - Voltages are with respect to VSS=0V unless otherwise stated
Parameter
Sym Min
TypMax Units Test Conditions
1 Positive Power Supply
VDD 4.75
5.0 5.25 V
2 Oscillator Clock Frequency
fOSC
3.579
MHz
3 Oscillator Frequency Tolerance
fOSC
±0.1 %
4 Operating Temperature
Td -40
25 85 °C
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to VDD=5V±5%,VSS=0V, and temperature -40 to 85°C, unless
otherwise stated.
Characteristics
Sym Min TypMax Units
Test Conditions
1 Operating supply current
2 Standby supply current
IDD
IDDQ
3 8 mA
30 100 µA PWDN=5V, ACK=0V
ESt/DStD = SD = 0V
3a Input logic 1
3b Input logic 1
(for OSC1 input only)
VIH 4.0
VIH 3.5
V
V ZL4902x/ZL4903x
4a Input logic 0
4b Input logic 0
(for OSC1 input only)
VIL
VIL
1.0 V
1.5 V ZL4902x/ZL4903x
5 Input impedance (pin 1)
6 Pull-down Current
(PWDN, ACK pins)
RIN 50
IPD
25
k
µA with internal pull-down
resistor of approx.
200k. PWDN/ACK =
5V
7 Output high (source) current
IOH 0.4 4.0
mA VOUT=VDD-0.4V
8 Output low (sink) current
IOL 1.0 9.0
mA VOUT=VSS+0.4V
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing
7
Zarlink Semiconductor Inc.

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