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PDF AD9983A Data sheet ( Hoja de datos )
| Número de pieza | AD9983A | |
| Descripción | High Performance 8-Bit Display Interface | |
| Fabricantes | Analog Devices | |
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Preliminary Technical Data
FEATURES
8-bit analog-to-digital converters
170 MSPS maximum conversion rate
Low PLL clock jitter at 170 MSPS
Automatic gain matching
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
External clock input
Regenerated Hsync output
Programmable output high impedance control
Hsyncs per Vsync counter
Sync-on-green pulse filter
Pb-free package
APPLICATIONS
Advanced TVs
Plasma display panels
LCDTV
HDTV
RGB graphics processing
LCD monitors and projectors
Scan converters
GENERAL DESCRIPTION
The AD9983A is a complete 8-bit, 170 MSPS, monolithic
analog interface optimized for capturing YPbPr video and RGB
graphics signals. Its 170 MSPS encode rate capability and full
power analog bandwidth of 300 MHz support all HDTV video
modes up to 1080p as well as graphics resolutions up to UXGA
(1600 x 1200 at 60 Hz).
The AD9983A includes a 170 MHz triple ADC with an internal
reference, a PLL, and programmable gain, offset, and clamp
control. The user provides only a 1.8 V power supply and an
analog input. Three-state CMOS outputs can be powered from
1.8 V to 3.3 V.
The AD9983A on-chip PLL generates a sample clock from the
tri-level sync (for YPbPr video) or the horizontal sync (for RGB
graphics). Sample clock output frequencies range from 10 MHz
to 170 MHz. With internal coast generation, the PLL maintains
its output frequency in the absence of sync input. A 32-step
High Performance
8-Bit Display Interface
AD9983A
FUNCTIONAL BLOCK DIAGRAM
AD9983A
8 AUTO OFFSET
Pr/REDIN1
Pr/REDIN0
2:1
MUX
AUTO GAIN
CLAMP
PGA
8-BIT
ADC
8 AUTO OFFSET
Y/GREENIN1
Y/GREENIN0
2:1
MUX
AUTO GAIN
CLAMP
PGA
8-BIT
ADC
8 AUTO OFFSET
Pb/BLUEIN1
Pb/BLUEIN0
2:1
MUX
CLAMP
AUTO GAIN
PGA
8-BIT
ADC
8 Cb/Cr/REDOUT
8
Y/GREENOUT
8
Cb/BLUEOUT
HSYNC1
HSYNC0
VSYNC0
VSYNC1
SOGIN1
SOGIN0
EXTCK/COAST
CLAMP
FILT
SDA
SCL
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
PLL
POWER
MANAGEMENT
SERIAL REGISTER
DATACK
SOGOUT
O/E FIELD
HSOUT
VSOUT/A0
VOLTAGE
REFS
REFHI
REFLO
Figure 1.
sampling clock phase adjustment is provided. Output data,
sync, and clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore
the signal reference levels and to automatically calibrate out any
offset differences between the three channels. The auto channel-
to-channel gain matching feature can be enabled to minimize
any gain mismatches between the three channels.
The AD9983A also offers full sync processing for composite
sync and sync-on-green applications. A clamp signal is
generated internally or may be provided by the user through the
CLAMP input pin.
Fabricated in an advanced CMOS process, the AD9983A is
provided in a space-saving 80-lead, Pb-free, LQFP surface-
mount plastic package or a 64-lead LFCSP package, and is
specified over the 0°C to 70°C temperature range.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
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Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VD
VDD
PVD
DAVDD
Analog Inputs
REFHI
REFLO
Digital Inputs
Digital Output Current
Operating Temperature
Storage Temperature
Maximum Junction Temperature
Maximum Case Temperature
Rating
1.98 V
3.6 V
1.98 V
1.98 V
VD to 0.0 V
VD to 0.0 V
VD to 0.0 V
5 V to 0.0 V
20 mA
−25°C to + 85°C
−65°C to + 150°C
150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD9983A
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
θJA θJC Unit
80-lead LQFP
35 16 °C/W
64-lead LFCSP
35 16 °C/W
ESD CAUTION
Rev. PrA | Page 5 of 44
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Preliminary Technical Data
AD9983A
THEORY OF OPERATION
The AD9983A is a fully integrated solution for capturing analog
RGB or YPbPr signals and digitizing them for display on
advanced TVs, flat panel monitors, projectors, and other types
of digital displays. Implemented in a high performance CMOS
process, the interface can capture signals with pixel rates of up
to 170 MHz.
The AD9983A includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface (I2C). Full integration of these sensitive
analog functions makes system design straightforward and less
sensitive to the physical and electrical environment.
With a typical power dissipation of less than 900 mW and an
operating temperature range of 0°C to 70°C, the device requires
no special environmental considerations.
DIGITAL INPUTS
All digital inputs on the AD9983A operate to 3.3 V CMOS
levels. The following digital inputs are 5 V tolerant (that is, applying
5 V to them does not cause any damage.): HSYNC0, HSYNC1,
VSYNC0, VSYNC1, SOGIN0, SOGIN1, SDA, SCL and CLAMP.
ANALOG INPUT SIGNAL HANDLING
The AD9983A has six high impedance analog input pins for the
red, green, and blue channels. They accommodate signals
ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board with a
DVI-I connector, a 15-pin D connector, or RCA connectors.
The AD9983A should be located as close as possible to the
input connector. Signals should be routed using matched-
impedance traces (normally 75 Ω) to the IC input pins.
At the input pins the signal should be resistively terminated
(75 Ω to the signal ground return) and capacitively coupled to
the AD9983A inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal
bandwidth. The wide bandwidth inputs of the AD9983A
(300 MHz) can track the input signal continuously as it moves
from one pixel level to the next and can digitize the pixel during
a long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. A small inductor in series with the input is
effective in rolling off the input bandwidth slightly and
providing a high quality signal over a wider range of conditions.
Using a Fair-Rite #2508051217Z0-High Speed, Signal Chip
Bead Inductor in the circuit shown in Figure 4 provides good
results in most applications.
RGB
INPUT
47nF
75Ω
RAIN
GAIN
BAIN
Figure 4. Analog Input Interface Circuit
HSYNC AND VSYNC INPUTS
The interface also accepts Hsync and Vsync signals, which are
used to generate the pixel clock, clamp timing, coast and field
information. These can be either a sync signal directly from the
graphics source, or a preprocessed TTL- or CMOS-level signal.
The Hsync input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no
termination is required.
SERIAL CONTROL PORT
The serial control port is designed for 3.3 V logic; however, it is
tolerant of 5 V logic signals. Refer to the 2-Wire Serial Control
Port section.
OUTPUT SIGNAL HANDLING
The digital outputs operate from 1.8 V to 3.3 V (VDD).
CLAMPING
RGB Clamping
To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board ADCs.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground, black is at 300 mV, and white is at approximately 1.0 V.
Some common RGB line amplifier boxes use emitter-follower
buffers to split signals and increase drive capability. This
introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9983A.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
offset is then introduced that results in the ADC producing a
black output (Code 0x00) when the known black input is
present. The offset then remains in place when other signal
levels are processed, and the entire signal is shifted to eliminate
offset errors.
Rev. PrA | Page 11 of 44
11 Page | ||
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