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CS4124 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 CS4124은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 CS4124 기능
기능 High Side PWM FET Controller
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CS4124 데이터시트, 핀배열, 회로
www.DataSheet4U.com
CS4124
High Side PWM FET
Controller
The CS4124 is a monolithic integrated circuit designed primarily to
control the rotor speed of permanent magnet, direct current (DC)
brush motors. It drives the gate of an N channel power MOSFET or
IGBT with a user–adjustable, fixed frequency, variable duty cycle,
pulse width modulated (PWM) signal. The CS4124 can also be used to
control other loads such as incandescent bulbs and solenoids.
Inductive current from the motor or solenoid is recirculated through an
external diode.
The CS4124 accepts a DC level input signal of 0 to 5.0 V to control
the pulse width of the output signal. This signal can be generated by a
potentiometer referenced to the on–chip 5.0 V linear regulator, or a
filtered 0% to 100% PWM signal also referenced to the 5.0 V
regulator.
The IC is placed in a sleep state by pulling the CTL lead below 0.5 V.
In this mode everything on the chip is shutdown except for the on–chip
regulator and the overall current draw is less than 275 µA. There are a
number of on–chip diagnostics that look for potential failure modes
and can disable the external power MOSFET.
Features
150 mA Peak PWM Gate Drive Output
Patented Voltage Compensation Circuit
100% Duty Cycle Capability
5.0 V, ± 3.0% Linear Regulator
Low Current Sleep Mode
Overvoltage Protection
Boost Mode Power Supply
Output Inhibit
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16
1
DIP–16
N SUFFIX
CASE 648
PIN CONNECTION AND
MARKING DIAGRAM
1
OUTPUT
BOOST
FLT
ROSC
COSC
CTL
PGND
VCC
16
GND
INH
IADJ
ISENSE+
ISENSE–
PMP
SNI
VREG
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION*
Device
Package
Shipping
CS4124YN16
DIP–16
25 Units/Rail
* Contact your local sales representative for 16-lead SOIC wide package.
© Semiconductor Components Industries, LLC, 2000
November, 2000 – Rev. 6
1
Publication Order Number:
CS4124/D




CS4124 pdf, 반도체, 판매, 대치품
CS4124
ELECTRICAL CHARACTERISTICS (continued) (4.0 V VCC 26 V; –40°C < TJ < 125°C; unless otherwise specified.)
Characteristic
Test Conditions
Min Typ Max
External Drive (OUTPUT) (continued)
Output Sink Current
Output Source Current
Output High Voltage
Output Low Voltage
Charge Pump (DRV)
4.0 V VCC < 7.0 V:
RGATE = 6.0 , CGATE = 5.0 nF
7.0 V VCC 26 V:
RGATE = 6.0 , CGATE = 5.0 nF
4.0 V VCC < 7.0 V:
RGATE = 6.0 , CGATE = 5.0 nF
7.0 V VCC 26 V:
RGATE = 6.0 , CGATE = 5.0 nF
IOUT = 1.0 mA
IOUT = –1.0 mA
VBOOST = 1.7
150
300
150
300
1.3
Boost Voltage
VCC + 6.4
Unit
mA
mA
mA
mA
V
V
V
PIN FUNCTION DESCRIPTION
PACKAGE PIN #
16 Lead PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN SYMBOL
OUTPUT
BOOST
FLT
ROSC
COSC
CTL
PGND
VCC
VREG
SNI
PMP
ISENSE–
ISENSE+
IADj
INH
GND
FUNCTION
MOSFET gate drive.
Boost voltage.
Fault time out capacitor.
Oscillator resistor.
Oscillator capacitor.
Pulse width control input.
Power ground for on chip clamp.
Positive power supply input.
5.0 V linear regulator.
Sense inductor current.
Collector of boost power transistor.
Current sense minus.
Current sense plus.
Current limit adjust.
Output Inhibit.
Ground.
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CS4124 전자부품, 판매, 대치품
CS4124
APPLICATIONS INFORMATION
THEORY OF OPERATION
Oscillator
The IC sets up a constant frequency triangle wave at the
COSC lead whose frequency is related to the external
components ROSC and COSC, by the following equation:
Frequency
+
0.83
ROSC COSC
The peak and valley of the triangle wave are proportional
to VCC by the following:
VVALLEY + 0.1 VCC
VPEAK + 0.7 VCC
This is required to make the voltage compensation
function properly. In order to keep the frequency of the
oscillator constant the current that charges COSC must also
vary with supply. ROSC sets up the current which charges
COSC. The voltage across ROSC is 50% of VCC and
therefore:
IROSC + 0.5
VCC
ROSC
IROSC is multiplied by (2) internally and transferred to the
COSC lead. Therefore:
ICOSC
+"
VCC
ROSC
The period of the oscillator is:
T + 2COSC
VPEAK * VVALLEY
ICOSC
The ROSC and COSC components can be varied to create
frequencies over the range of 15 Hz to 25 kHz. With the
suggested values of 93.1 kand 470 pF for ROSC and COSC,
the nominal frequency will be approximately 20 kHz.
IROSC, at VCC = 14 V, will be 66.7 µA. IROSC should not
change over a more than 2:1 ratio and therefore COSC should
be changed to adjust the oscillator frequency.
Voltage Duty Cycle Conversion
The IC translates an input voltage at the CTL lead into a
duty cycle at the OUTPUT lead. The transfer function
incorporates ON Semiconductor’s patented Voltage
Compensation method to keep the average voltage and
current across the load constant regardless of fluctuations in
the supply voltage. The duty cycle is varied based upon the
input voltage and supply voltage by the following equation:
Duty Cycle + 100%
2.8 VCTL
VCC
An internal DC voltage equal to:
VDC + (1.683 VCTL) ) VVALLEY
is compared to the oscillator voltage to produce the
compensated duty cycle. The transfer is set up so that when
VCC = 14 V the duty cycle will equal VCTL divided by VREG.
For example at VCC = 14 V, VREG = 5.0 V and VCTL = 2.5 V,
the duty cycle would be 50% at the output. This would place
a 7.0 V average voltage across the load. If VCC then drops
to 10 V, the IC would change the duty cycle to 70% and
hence keep the average load voltage at 7.0 V.
120
100 VCC = 8.0 V
80
VCC = 14 V
60
40 VCC = 16 V
20
0
10 20 30 40 50 60 70 80 90 100
CTL Voltage (% of VREG)
Figure 7. Voltage Compensation
5.0 V Linear Regulator
There is a 5.0 V, 5.0 mA linear regulator available at the
VREG lead for external use. This voltage acts as a reference
for many internal and external functions. It has a drop out of
approximately 1.5 V at room temperature.
Current Sense and Timer
The IC differentially monitors the load current on a cycle
by cycle basis at the ISENSE+ and ISENSE– leads. The
differential voltage across these two leads is amplified
internally and compared to the voltage at the IADJ lead. The
gain, AV is set internally and externally by the following
equation:
AV
+
VI(ADJ)
ISENSE) * ISENSE*
+
37000
1000 ) RCS
The current limit (ILIM) is set by the external current sense
resistor (RSENSE) placed across the ISENSE+ and ISENSE–
terminals and the voltage at the IADJ lead.
ILIM
+
1000 ) RCS
37000
VI(ADJ)
RSENSE
The RCS resistors and CCS components form a differential
low pass filter which filters out high frequency noise
generated by the switching of the external MOSFET and the
associated lead noise. RCS also forms an error term in the
gain of the ILIM equation because the ISENSE+ and ISENSE–
leads are low impedance inputs thereby creating a good
current sensing amplifier. Both leads source 50 µA while the
chip is in run mode. IADJ should be biased between 1.0 V and
4.0 V. When the current through the external MOSFET
exceeds ILIM, an internal latch is set and the output pulls the
gate of the MOSFET low for the remainder of the oscillator
cycle (fault mode). At the start of the next cycle, the latch is
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