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CS5124 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 CS5124은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 CS5124 기능
기능 (CS5124 / CS5126) Integrated Current Mode PWM Controllers
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CS5124 데이터시트, 핀배열, 회로
www.DataSheet4U.com
CS5124, CS5126
High Performance,
Integrated Current Mode
PWM Controllers
The CS5124/6 is a fixed frequency current mode controller
designed specifically for DC−DC converters found in the
telecommunications industry. The CS5124/6 integrates many
commonly required current mode power supply features and allows
the power supply designer to realize substantial cost and board space
savings. The product matrix is as follows:
CS5124: 400 kHz w/VBIAS Pin, 195 mV first current sense threshold.
CS5126: 200 kHz w/SYNC Pin, 335 mV first current sense threshold.
The CS5124/6 integrates the following features: Internal Oscillator,
Slope Compensation, Sleep On/Off, Undervoltage Lock Out, Thermal
Shutdown, Soft−Start Timer, Low Voltage Current Sense for Resistive
Sensing, Second Current Threshold for Pulse−by−Pulse overcurrent
Protection, a Direct Optocoupler Interface and Leading Edge Current
Blanking.
The CS5124/6 has supply range of 7.7 V to 20 V and is available in
8 pin SOIC narrow package.
http://onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
PIN CONNECTIONS AND
MARKING DIAGRAM
1
VCC
BIAS
UVLO
SS
CS5124 8
GND
GATE
ISENSE
VFB
Features
Line UVLO Monitoring
Low Current Sense Voltage for Resistive Current Sensing
External Synchronization to Higher or Lower Frequency Oscillator
(CS5126 Only)
Bias for Startup Circuitry (CS5124 Only)
Thermal Shutdown
Sleep On/Off Pin
Soft−Start Timer
Leading Edge Blanking
Direct Optocoupler Interface
90 ns Propagation Delay
35 ns Driver Rise and Fall Times
Sleep Mode
Pb−Free Packages are Available
1
VCC
UVLO
SYNC
SS
CS5126 8
GND
GATE
ISENSE
VFB
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
CS5124XD8
SOIC−8
95 Units/Rail
CS5124XD8G
SOIC−8
(Pb−Free)
95 Units/Rail
CS5124XDR8
SOIC−8 2500 Tape & Reel
CS5124XDR8G SOIC−8 2500 Tape & Reel
(Pb−Free)
CS5126XD8
CS5126XDR8
SOIC−8
SOIC−8
95 Units/Rail
2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2005
September, 2005 − Rev. 6
1
Publication Order Number:
CS5124/D




CS5124 pdf, 반도체, 판매, 대치품
CS5124, CS5126
ELECTRICAL CHARACTERISTICS (continued) (−40°C TJ 125°C; −40°C TA 105°C, 7.60 V VCC 20 V, UVLO = 3.0 V,
ISENSE = 0 V, CV(CC) = 0.33 mF, CGATE = 1.0 nF (ESR = 10 W); CSS = 470 pF; CV(FB) = 100 pF, unless otherwise specified.)
Characteristic
Test Conditions
Min Typ Max Unit
Soft−Start
Soft−Start Charge Current
− 7.0 10
Soft−Start Discharge Current
− 0.5 10.0
VSS Voltage when VFB Begins to
Rise
VFB = 300 mV
1.40 1.62
Peak Soft−Start Charge Voltage
− 4.7 4.9
Valley Soft−Start Discharge Voltage
200 275
Current Sense
CS5124 Only
First Current Sense Threshold
At max duty cycle
170 195
Second Current Sense Threshold − 250 275
ISENSE to GATE Prop. Delay
Leading Edge Blanking Time
Internal Offset
0 to 700 mV pulse into ISENSE (after blanking time)
0 to 400 mV pulse into ISENSE
Note 3
60
90
90
130
60
Current Sense
CS5126 Only
First Current Sense Threshold
At max duty cycle
300 335
Second Current Sense Threshold
ISENSE to GATE Prop. Delay
Leading Edge Blanking Time
Internal Offset
0 to 800 mV pulse into ISENSE (after blanking time)
0 to 550 mV pulse into ISENSE
(Note 3)
485
60
110
525
90
175
125
Voltage Feedback
VFB Pull−up Res.
VFB Clamp Voltage
VFB Clamp Voltage
VFB Fault Voltage Threshold
Output Gate Drive
CS5124 Only
CS5126 Only
2.9 4.3
2.63 2.90
2.40 2.65
460 490
Maximum Sleep Pull−down Voltage
GATE High (AC)
GATE Low (AC)
VCC = 6.0 V, IOUT = 1.0 mA
Series resistance < 1.0 W, (Note 3)
Series resistance < 1.0 W, (Note 3)
− 1.2
VCC − 1.0 VCC − 0.5
− 0.0
GATE High Clamp Voltage
Rise Time
Fall TIme
VCC = 20 V
Measure GATE rise time,
1.0 V < GATE < 9.0 V VCC = 12 V
Measure GATE fall time,
9.0 V > GATE > 1.0 V VCC = 12 V
11.0 13.5
− 45
− 25
Thermal Shutdown
Thermal Shutdown Temperature
(Note 3) GATE low
135 150
Thermal Enable Temperature
(Note 3) GATE switching
100 125
Thermal Hysteresis
(Note 3)
15 25
3. Not tested in production. Specification is guaranteed by design.
13
1.80
400
215
315
130
180
360
575
130
210
8.1
3.15
290
520
2.0
0.5
16.0
65
55
165
150
35
mA
mA
V
V
mV
mV
mV
ns
ns
mV
mV
mV
ns
ns
mV
kW
V
V
mV
V
V
V
V
ns
ns
°C
°C
°C
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CS5124 전자부품, 판매, 대치품
CS5124, CS5126
Soft−Start
Soft−Start is accomplished by clamping the VFB pin 1.32 V
below the SS pin during normal start up and during restart
after a fault condition. When the CS5124/6 starts, the
Soft−Start capacitor is charged from a 10 mA source from 0
V to 4.9 V. The VFB pin follows the Soft−Start pin offset
by −1.32 V until the supply comes into regulation or until
the Soft−Start error amp is clamped at 2.9 V (2.65 V for the
CS5126). During fault conditions the Soft−Start capacitor is
discharged at 10 mA.
Fault Conditions
The CS5124/6 recognizes the following faults: UVLO
off, Thermal Shutdown, VREF(OK), and Second Current
Threshold. Once a fault is recognized, fault latch F2 is set
and the IC immediately shuts down the output driver and
discharges the Soft−Start capacitor. Soft−Start will begin
only after all faults have been removed and the Soft−Start
capacitor has been discharged to less than 0.275 V. Each
fault will be explained in the following sections.
Under Voltage Lockout (UVLO)
The UVLO pin is tied to typically the midpoint of a
resistive divider between VIN and GROUND. During a start
up sequence, this pin must be above 2.6 V in order for the IC
to begin normal operation. If the IC is running and this pin
is pulled below 1.8 V, F2 shuts down the output driver and
discharges the Soft−Start capacitor in order to insure proper
startup. If the UVLO pin is pulled high again before the
Soft−Start capacitor discharges, the IC will complete the
Soft−Start discharge and, if no other faults are present, will
immediately restart the power supply. If the UVLO pin stays
low, then it will enter either the low current sleep mode or the
UVLO state depending on the level of the UVLO pin.
Thermal Shutdown
If the IC junction temperature exceeds approximately
150°C the thermal shutdown circuit sets F2, which shuts
down the output driver and discharges the Soft−Start
capacitor. If no other faults are present the IC will initiate
Soft−Start when the IC junction temperature has been
reduced by 25°C.
VREF(OK)
VREF(OK) is an internal monitor that insures the internal
regulator is running before any switching occurs. This
function does not trip the fault comparator like the other fault
functions. To insure that Soft−Start will occur at low line
conditions the UVLO divider should be set up so that the
VCC UVLO comparator turns on before the LINE UVLO
comparator.
Second Threshold Comparator
Since the maximum dynamic range of the ISENSE signal
in normal operation is 195 mV (335 mV for the CS5126),
any voltage exceeding this threshold on the ISENSE pin is
considered a fault and the PWM cycle is terminated. The 2nd
ICOMP compares the ISENSE signal with a 275 mV (525 mV
for the CS5126) threshold. If the ISENSE voltage exceeds the
second threshold, F2 is set, the driver turns off, and the
Soft−Start capacitor discharges. After the Soft−Start
capacitor has discharged to less than 0.275 V Soft−Start will
begin. If the fault condition has been removed the supply
will operate normally. If the fault remains the supply will
operate in hiccup mode until the fault condition is removed.
VFB Comparator
The VFB comparator detects when the output voltage is
too high. When the regulated output voltage is too high, the
feedback loop will drive VFB low. If VFB is less than 0.49 V
the output of the VFB comparator will go high and shut the
output driver off.
Oscillator
The internally trimmed, 400 kHz (CS5124) or 200 kHz
(CS5126) provides the slope compensation ramp as well as
the pulse for enabling the output driver.
PWM Comparator and Slope Compensation
The CS5124/6 provides a fixed internal slope
compensation ramp that is subtracted from the feedback
signal. The PWM comparator compares peak primary
current to a portion of the difference of the feedback voltage
and slope compensation ramp. The 170 mV/ms (85 mV/ms
for the CS5126) slope compensation ramp is subtracted
from the voltage feedback signal internally. The difference
signal is then divided by ten (five for the CS5126) before the
PWM comparator to provide high noise rejection with a low
voltage across the current sense network. (The effective
ramp is 21 mV/ms for the CS5124, and 18 mV/ms for the
CS5126). A 60 mV (125 mV for the CS5126) nominal offset
on the positive input to the PWM comparator allows for
operation with the ISENSE pin at, or even slightly below
GND.
A 4.3 kW pull−up resistor internally connected to a 5.0 V
nominal reference provides the bias current to for an
optocoupler connection to the VFB pin.
http://onsemi.com
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