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PDF CS5126 Data sheet ( Hoja de datos )
| Número de pieza | CS5126 | |
| Descripción | (CS5124 / CS5126) Integrated Current Mode PWM Controllers | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CS5126 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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CS5124, CS5126
High Performance,
Integrated Current Mode
PWM Controllers
The CS5124/6 is a fixed frequency current mode controller
designed specifically for DC−DC converters found in the
telecommunications industry. The CS5124/6 integrates many
commonly required current mode power supply features and allows
the power supply designer to realize substantial cost and board space
savings. The product matrix is as follows:
CS5124: 400 kHz w/VBIAS Pin, 195 mV first current sense threshold.
CS5126: 200 kHz w/SYNC Pin, 335 mV first current sense threshold.
The CS5124/6 integrates the following features: Internal Oscillator,
Slope Compensation, Sleep On/Off, Undervoltage Lock Out, Thermal
Shutdown, Soft−Start Timer, Low Voltage Current Sense for Resistive
Sensing, Second Current Threshold for Pulse−by−Pulse overcurrent
Protection, a Direct Optocoupler Interface and Leading Edge Current
Blanking.
The CS5124/6 has supply range of 7.7 V to 20 V and is available in
8 pin SOIC narrow package.
http://onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
PIN CONNECTIONS AND
MARKING DIAGRAM
1
VCC
BIAS
UVLO
SS
CS5124 8
GND
GATE
ISENSE
VFB
Features
• Line UVLO Monitoring
• Low Current Sense Voltage for Resistive Current Sensing
• External Synchronization to Higher or Lower Frequency Oscillator
(CS5126 Only)
• Bias for Startup Circuitry (CS5124 Only)
• Thermal Shutdown
• Sleep On/Off Pin
• Soft−Start Timer
• Leading Edge Blanking
• Direct Optocoupler Interface
• 90 ns Propagation Delay
• 35 ns Driver Rise and Fall Times
• Sleep Mode
• Pb−Free Packages are Available
1
VCC
UVLO
SYNC
SS
CS5126 8
GND
GATE
ISENSE
VFB
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
CS5124XD8
SOIC−8
95 Units/Rail
CS5124XD8G
SOIC−8
(Pb−Free)
95 Units/Rail
CS5124XDR8
SOIC−8 2500 Tape & Reel
CS5124XDR8G SOIC−8 2500 Tape & Reel
(Pb−Free)
CS5126XD8
CS5126XDR8
SOIC−8
SOIC−8
95 Units/Rail
2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2005
September, 2005 − Rev. 6
1
Publication Order Number:
CS5124/D
1 page  
CS5124, CS5126
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
CS5124 CS5126
11
2−
Pin
VCC
BIAS
Description
VCC Power Input Pin.
VCC Clamp Output Pin. This pin will control the gate of an N−channel MOSFET that in turn regulates Vcc.
This pin is internally clamped at 15 V when the IC is in sleep mode.
− 3 SYNC Clock Synchronization Pin. A positive edge will terminate the current PWM cycle. Ground this pin when it
is not used.
3 2 UVLO Sleep and under voltage lockout pin. A voltage greater than 1.8 V causes the chip to “wake up” however
the GATE remains low. A voltage greater than 2.6 V on this pin allows the output to switch.
4 4 SS Soft−Start Capacitor Pin. A capacitor placed between SS and GROUND is charged with 10 mA and dis-
charged with 10 mA. The Soft−Start capacitor controls both Soft−Start time and hiccup mode frequency.
5 5 VFB Voltage Feedback Pin. The collector of an optocoupler is typically tied to this pin. This pin is pulled up
internally by a 4.3 kW resistor to 5.0 V and is clamped internally at 2.9 V (2.65 V). If VFB is pulled > 4.0 V,
the oscillator is disabled and GATE will stay high. If the VFB pin is pulled < 0.49 V, GATE will stay low.
6 6 ISENSE Current Sense Pin. This pin is connected to the current sense resistor on the primary side. If VFB is float-
ing, the GATE will go low if ISENSE = 195 mV (335 mV). If ISENSE > 275 mV (525 mV), Soft−Start will be
initiated.
7 7 GATE Gate Drive Output Pin. Capable of driving a 3.0 nF load. GATE is nominally clamped to 13.5 V.
8 8 GND Ground Pin.
http://onsemi.com
5
5 Page 
CS5124, CS5126
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AG
−X−
A
B
−Y−
−Z−
H
85
S 0.25 (0.010) M Y M
1
4
K
G
D
C
SEATING
PLANE
N X 45 _
0.10 (0.004)
M
0.25 (0.010) M Z Y S X S
J
SOLDERING FOOTPRINT*
1.52
0.060
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0_ 8_ 0_ 8_
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
ǒ ǓSCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
PACKAGE THERMAL DATA
RqJC
RqJA
Parameter
Typical
Typical
SOIC−8
45
165
Unit
°C/W
°C/W
http://onsemi.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CS5126.PDF ] | |
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