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CS5165 데이터시트 PDF




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부품번호 CS5165 기능
기능 CPU 5-Bit Synchronous Buck Controller
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CS5165 데이터시트, 핀배열, 회로
www.DataSheet4U.com
CS5165
5−Bit Synchronous CPU
Buck Controller
The CS5165 synchronous 5bit NFET buck controller is optimized to
manage the power of the next generation Pentium II processors. It’s
V2control architecture delivers the fastest transient response (100 ns),
and best overall voltage regulation in the industry today. It’s feature rich
design gives end users the maximum flexibility to implement the best
price/performance solutions for their end products.
The CS5165 has been carefully crafted to maximize performance and
protect the processor during operation. It has a 5bit DAC on board that
holds a ±1.0% tolerance over temperature. Its on board programmable
Soft Start insures a control start up, and the FET nonoverlap circuitry
ensures that both FETs do not conduct simultaneously.
The on board oscillator can be programmed up to 1.0 MHz to give
the designer maximum flexibility in choosing external components
and setting systems costs.
The CS5165 protects the processor during potentially catastrophic
events like overvoltage (OVP) and short circuit. The OVP feature is
part of the V2 architecture and does not require any additional
components. During short circuit, the controller pulses the MOSFETs
in a “hiccup” mode (3.0% duty cycle) until the fault is removed. With
this method, the MOSFETs do not overheat or self destruct.
The CS5165 is designed for use in both single processor desktop and
multiprocessor workstation and server applications. The CS5165’s
current sharing capability allows the designer to build multiple
parallel and redundant power solutions for multiprocessor systems.
The CS5165 contains other control and protection features such as
Power Good, ENABLE, and adaptive voltage positioning. It is
available in a 16 lead SOIC wide body package.
Features
V2 Control Topology
Dual NChannel Design
100 ns Controller Transient Response
Excess of 1.0 MHz Operation
5Bit DAC with 1.0% Tolerance
Power Good Output With Internal Delay
Enable Input Provides Micropower Shutdown Mode
5.0 V & 12 V Operation
Adaptive Voltage Positioning
Remote Sense Capability
Current Sharing Capability
VCC Monitor
Hiccup Mode Short Circuit Protection
Overvoltage Protection (OVP)
Programmable Soft Start
150 ns PWM Blanking
65 ns FET Nonoverlap Time
40 ns Gate Rise and Fall Times (3.3 nF Load)
© Semiconductor Components Industries, LLC, 2001
July, 2006 Rev. 4
1
http://onsemi.com
16
1
SO16L
DW SUFFIX
CASE 751G
MARKING
DIAGRAM
16
CS5165
AWLYYWW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
1
VID0
VID1
VID2
VID3
SS
VID4
COFF
ENABLE
16
VFB
COMP
LGND
PWRGD
GATE(L)
PGND
GATE(H)
VCC
ORDERING INFORMATION
Device
CS5165GDW16
CS5165GDWR16
Package
Shipping
SO16L 46 Units/Rail
SO16L 1000 Tape & Reel
Publication Order Number:
CS5165/D




CS5165 pdf, 반도체, 판매, 대치품
CS5165
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC < 14 V; 2.8 DAC Code:
(VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0); CGATE(H) and CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 μF, unless otherwise specified.)
Characteristic
Test Conditions
Min Typ Max Unit
Fault Protection
SS Charge Time
SS Pulse Period
SS Duty Cycle
VFB = 0 V
VFB = 0 V
(Charge Time/Period) × 100
1.6 3.3 5.0 ms
25 100 200 ms
1.0 3.3 6.0 %
SS COMP Clamp Voltage
VFB Low Comparator
PWM Comparator
VFB = 2.7 V; VSS = 0 V
Increase VFB till no SS pulsing and normal Offtime
0.50
0.9
0.95
1.0
1.10
1.1
V
V
Transient Response
VFB = 1.2 to 5.0 V. 500 ns after GATE(H)
(after Blanking time) to GATE(H) = (VCC 1.0 V)
to 1.0 V
100 150 ns
Minimum Pulse Width
(Blanking Time)
Drive VFB. 1.2 to 5.0 V upon GATE(H) rising edge
(> VCC 1.0 V), measure GATE(H) pulse width
50
150 250 ns
COFF
Normal OffTime
Extended OffTime
TimeOut Timer
VFB = 2.7 V
VSS = VFB = 0 V
1.0 1.6 2.3 μs
5.0 8.0 12.0 μs
TimeOut Time
Fault Duty Cycle
Enable Input
VFB = 2.7 V, Measure GATE(H) Pulse Width
VFB = 0V
10 30 50 μs
30 50 70 %
ENABLE Threshold
GATE(H) Switching
0.8 1.15 1.30 V
Shutdown delay (Note 3)
ENABLEtoGATE(H) < 2.0 V
3.0 μs
Pullup Current
ENABLE = 0 V
3.0 7.0 15 μA
Pullup Voltage
No load on ENABLE pin
1.30 1.8 3.0 V
Input Resistance
Power Good Output
ENABLE = 5.0 V, R = (5.0 V VPULLUP)/IENABLE
10
20
50 kΩ
Low to High Delay
VFB = (0.8 × VDAC) to VDAC
High to Low Delay
VFB = VDAC to (0.8 × VDAC)
Output Low Voltage
VFB = 2.4 V, IPWRGD = 500 μA
Sink Current Limit
VFB = 2.4 V, PWRGD = 1.0 V
3. Guaranteed by design, not 100% tested in production.
30 65 110 μs
30 75 120 μs
0.2 0.3 V
0.5 4.0 15.0 mA
http://onsemi.com
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CS5165 전자부품, 판매, 대치품
PACKAGE PIN #
SO16L
1, 2, 3, 4, 6
5
7
8
9
10
11
12
13
14
15
16
CS5165
PACKAGE PIN DESCRIPTION
PIN SYMBOL
VID0VID4
SS
COFF
ENABLE
VCC
GATE(H)
PGND
GATE(L)
PWRGD
LGND
COMP
VFB
FUNCTION
Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V if left open. VID4
selects the DAC range. When VID4 is high (logic one), the Error Amp reference range is
2.14 V to 3.45 V with 100 mV increments. When VID4 is low (logic zero), the Error Amp
reference voltage 1.34 V to 2.09 V with 50 mV increments.
Soft Start Pin. A capacitor from this pin to LGND sets the Soft Start and fault timing.
OffTime Capacitor Pin. A capacitor from this pin to LGND sets both the normal and
extended off time.
Output Enable Input. This pin is internally pulled up to 1.8 V. A logic Low (< 0.8) on this
pin disables operation and places the CS5165 into a low current sleep mode.
Input Power Supply Pin.
High Side Switch FET driver pin.
High current ground for the GATE(H) and GATE(L) pins.
Low Side Synchronous FET driver pin.
Power Good Output. Open collector output drives low when VFB is out of regulation. Ac-
tive when ENABLE input is low.
Reference ground. All control circuits are referenced to this pin.
Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error
Amp compensation.
Error Amp, PWM Comparator, and Low VFB Comparator feedback input.
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