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BUB323Z PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BUB323Z
기능 NPN Silicon Power Darlington
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BUB323Z 데이터시트, 핀배열, 회로
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BUB323Z
NPN Silicon Power
Darlington
High Voltage Autoprotected
D2PAK for Surface Mount
The BUB323Z is a planar, monolithic, high–voltage power
Darlington with a built–in active zener clamping circuit. This device is
specifically designed for unclamped, inductive applications such as
Electronic Ignition, Switching Regulators and Motor Control, and
exhibit the following main features:
Integrated High–Voltage Active Clamp
Tight Clamping Voltage Window (350 V to 450 V) Guaranteed
Over the –40°C to +125°C Temperature Range
Clamping Energy Capability 100% Tested in a Live
Ignition Circuit
High DC Current Gain/Low Saturation Voltages
Specified Over Full Temperature Range
Design Guarantees Operation in SOA at All Times
MAXIMUM RATINGS
Rating
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCollector–Emitter Sustaining Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCollector–Emitter Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCollector Current – Continuous
– Peak
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎBase Current
– Continuous
– Peak
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Power Dissipation
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ@ TC = 25_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDerate above 25_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOperating and Storage Junction
Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTHERMAL CHARACTERISTICS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎThermal Resistance, Junction to Case
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎThermal Resistance, Junction to Ambient
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaximum Lead Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎfor Soldering Purposes,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1/8from Case for 5 Seconds
Symbol
VCEO
VEBO
IC
ICM
IB
IBM
PD
TJ, Tstg
Symbol
RθJC
RθJA
TL
Value
350
6.0
10
20
3.0
6.0
150
1.0
–65 to
+175
Max
1.0
62.5
260
Unit
Vdc
Vdc
Adc
Adc
Watts
W/_C
_C
Unit
_C/W
_C/W
_C
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AUTOPROTECTED
DARLINGTON
10 AMPERES
360–450 VOLTS CLAMP
150 WATTS
360 V
CLAMP
MARKING DIAGRAM
D2PAK
CASE 418B
STYLE 1
BUB323Z
YWW
BUB323Z = Specific Device Code
Y = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
BUB323Z
D2PAK
50 Units/Rail
BUB323ZT4
D2PAK 800/Tape & Reel
© Semiconductor Components Industries, LLC, 2001
September, 2001 – Rev. 0
1
Publication Order Number:
BUB323Z/D




BUB323Z pdf, 반도체, 판매, 대치품
ICPEAK
IC
ICPEAK
IC
(a)
BUB323Z
IC HIGH
IC LOW
VCE
VGATE MIN
The shaded area represents the amount of energy the de-
vice can sustain, under given DC biases (IC/IB/VBE(off)/
RBE), without an external clamp; see the test schematic dia-
gram, Figure 2. .
The transistor PASSES the Energy test if, for the inductive
load and ICPEAK/IB/VBE(off) biases, the VCE remains outside
the shaded area and greater than the VGATE minimum limit,
Figure 4. a.
IC HIGH
ICPEAK
IC
(b)
IC LOW
VCE
VGATE MIN
IC HIGH
The transistor FAILS if the VCE is less than the VGATE
(minimum limit) at any point along the VCE/IC curve as
shown on Figures 4. b, and 4. c. This assures that hot spots
and uncontrolled avalanche are not being generated in the
die, and the transistor is not damaged, thus enabling the sus-
tained energy level required.
ICPEAK
IC
(c)
IC LOW
VCE
VGATE MIN
IC HIGH
The transistor FAILS if its Collector/Emitter breakdown
voltage is less than the VGATE value, Figure 4. d.
IC LOW
VCE
(d) VGATE MIN
Figure 4. Energy Test Criteria for BU323Z
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BUB323Z 전자부품, 판매, 대치품
BUB323Z
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143,
SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the Collector pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 12. shows a
typical stencil for the DPAK and D2PAK packages. The
pattern of the opening in the stencil for the Collector pad is
not critical as long as it allows approximately 50% of the
pad to be covered with paste.
ÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇSOLDER PASTE
ÇÇOPENINGS
STENCIL
Figure 12. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* Due to shadowing and the inability to set the wave height
to incorporate other surface mount components, the D2PAK
is not recommended for wave soldering.
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BUB323Z

NPN Silicon Power Darlington

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