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PDF CS51221 Data sheet ( Hoja de datos )
| Número de pieza | CS51221 | |
| Descripción | Enhanced Voltage Mode PWM Controller | |
| Fabricantes | ON Semiconductor | |
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CS51221
Enhanced Voltage Mode
PWM Controller
The CS51221 fixed frequency feed forward voltage mode PWM
controller contains all of the features necessary for basic voltage mode
operation. This PWM controller has been optimized for high
frequency primary side control operation. In addition, this device
includes such features as: Soft−Start, accurate duty cycle limit control,
less than 50mA startup current, over and undervoltage protection, and
bidirectional synchronization. The CS51221 is available in a 16 lead
SOIC narrow surface mount package.
Features
• 1.0 MHz Frequency Capability
• Fixed Frequency Voltage Mode Operation, with Feed Forward
• Thermal Shutdown
• Undervoltage Lock−Out
• Accurate Programmable Max Duty Cycle Limit
• 1.0 A Sink/Source Gate Drive
• Programmable Pulse−By−Pulse Overcurrent Protection
• Leading Edge Current Sense Blanking
• 75 ns Shutdown Propagation Delay
• Programmable Soft−Start
• Undervoltage Protection
• Overvoltage Protection with Programmable Hysteresis
• Bidirectional Synchronization
• 25 ns GATE Rise and Fall Time (1.0 nF Load)
• 3.3 V 3% Reference Voltage Output
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
September, 2005 − Rev. 8
1
http://onsemi.com
16
1
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DTB SUFFIX
16 CASE 948F
1
PIN CONNECTIONS AND
MARKING DIAGRAM
1
GATE
ISENSE
SYNC
FF
UV
OV
16
VC
PGND
VCC
VREF
LGND
SS
RTCT
ISET
COMP
VFB
1 16
CS51221= Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package Shipping†
CS51221ED16
SOIC−16 48 Units / Rail
CS51221ED16G
CS51221EDR16
SOIC−16 48 Units / Rail
(Pb−Free)
SOIC−16 2500 Tape & Reel
CS51221EDR16G
CS51221EDTB16G
SOIC−16 2500 Tape & Reel
(Pb−Free)
TSSOP−16 96 Units / Rail
(Pb−Free)
CS51221EDTB16R2G TSSOP−16 2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
CS51221/D
1 page  
CS51221
ELECTRICAL CHARACTERISTICS (−40°C < TA < 85°C; −40°C < TJ < 125°C; 3.0 V < VC < 15 V; 4.7 V < VCC < 15 V;
RT = 12 k; CT = 390 pF; unless otherwise specified.)
Characteristic
Test Conditions
Min Typ
Max
Gate Driver
High Saturation Voltage
Low Saturation Voltage
High Voltage Clamp
VC − GATE, VC = 10 V, ISOURCE = 200 mA
GATE − PGND, ISINK = 200 mA
−
− 1.5 2.0
− 1.2 1.5
11 13.5
16
Output Current
Output UVL Leakage
1.0 nF Load. Note 3
GATE = 0 V
− 1.0 1.25
− 1.0 50
Rise Time
Fall Time
Max Gate Voltage During UVL/Sleep
Feed Forward (FF)
1.0 nF Load, VC = 20 V, 1.0 V < GATE < 9.0 V
1.0 nF Load, VC = 20 V, 9.0 V < GATE < 1.0 V
IGATE = 500 mA
−
−
0.4
60
25
0.7
100
50
1.0
Discharge Voltage
Discharge Current
FF to GATE Delay
IFF = 2.0 mA
FF = 1.0 V
−
− 0.3
2.0 16
50 75
0.7
30
125
Overcurrent Protection
Overcurrent Threshold
ISENSE to GATE Delay
External Voltage Monitors
ISET = 0.5 V, Ramp ISENSE
−
0.475
50
0.5
90
0.525
125
Overvoltage Threshold
OV Increasing
1.9 2.0
2.1
Overvoltage Hysteresis Current
Undervoltage Threshold
OV = 2.15 V
UV Increasing
10 12.5
0.95 1.0
15
1.05
Undervoltage Hysteresis
− 25 75 125
Soft−Start (SS)
Charge Current
Discharge Current
SS = 2.0 V
SS = 2.0 V
40 50
4.0 5.0
70
7.0
Charge Voltage
−
2.8 3.0
3.4
Discharge Voltage
Soft−Start Clamp Offset
FF = 1.25 V
−
0.25 0.3
1.15 1.25
0.35
1.35
Soft−Start Fault Voltage
OV = 2.15 V or LV = 0.85 V
− 0.1 0.2
Blanking
Blanking Time
SS Blanking Disable Threshold
COMP Blanking Disable Threshold
Thermal Shutdown
−
VFB < 1.0
VFB < 1.0, SS > 3.0 V
50 150
2.8 3.0
2.8 3.0
250
3.3
3.3
Thermal Shutdown
Note 3
125 150
180
Thermal Hysteresis
Note 3
5.0 10
15
3. Guaranteed by design, not 100% tested in production.
Unit
V
V
V
A
mA
ns
ns
V
V
mA
ns
V
ns
V
mA
V
mV
mA
mA
V
V
V
V
ns
V
V
°C
°C
http://onsemi.com
5
5 Page 
CS51221
800
700
600
RT = 5.0 K
500
400
RT = 10 K
300
200
100
0
0.0001
RT = 50 K
0.001
CT (mF)
0.01
Figure 10. Typical Performance Characteristics,
Oscillator Frequency vs. CT
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
1000
10000
100000
RT (W)
1000000
Figure 11. Typical Performance Characteristics,
Oscillator Duty Cycle vs. RT
that during steady state, VCOMP doesn’t change for input
voltage variations. This intuitively explains why FF voltage
mode control has superior line regulation and line transient
response. Knowing the nominal value of VIN and TON, one
can also select the value of RC to place VCOMP at the center
of its dynamic range.
Select Feedback Voltage Divider
As shown in Figure 12, the voltage divider output feeds to
the FB pin, which connects to the inverting input of the error
amplifier. The non−inverting input of the error amplifier is
connected to a 1.27 V (typ) reference voltage. The FB pin
has an input current which has to be considered for accurate
DC outputs. The following equation can be used to calculate
the R1 and R2 value
ǒ ǓR2
R1 ) R2
VOUT
+ 1.27 * ʼn
where ∇ is the correction factor due to the existence of the
FB pin input current Ier.
ʼn + (Ri ) R1ńńR2)Ier
Ri = DC resistance between the FB pin and the voltage
divider output.
Ier = VFB input current, 1.3 mA typical.
Design Voltage Dividers for OV and UV Detection
In Figure 13, the voltage divider uses three resistors in
series to set OV and UV threshold seen from the input
voltage. The values of the resistors can be calculated from
the following three equations, where the third equation is
derived from OV hysteresis requirement.
ǒ ǓVIN(LOW)
R2 ) R3
R2 ) R3 ) R1
+ 1.0 V
(A)
ǒ ǓVIN(HIGH)
R3
R2 ) R3 ) R1
+ 2.0 V
(B)
12.5 mA (R1 ) R2) + VHYST
(C)
where:
VIN(LOW), VIN(HIGH) = input voltage OV and UV
threshold;
VHYST = OV hysteresis seen at VIN
It is self−evident from equation A and B that to use this
design, VIN(HIGH) has to be two times greater than
VIN(LOW). Otherwise, two voltage dividers have to be used
to program OV and UV separately.
COMP
VOUT
Ier R1
− Ri
FB
+
+
−
1.27
R2
Figure 12. The Design of Feedback Voltage Divider
Has to Consider the Error Amplifier Input Current
R1 R2 R3
VIN
VUV
VOV
Figure 13. OV/UV Monitor Divider
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11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CS51221.PDF ] | |
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