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PDF CS51311 Data sheet ( Hoja de datos )
| Número de pieza | CS51311 | |
| Descripción | Synchronous CPU Buck Controller | |
| Fabricantes | ON Semiconductor | |
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CS51311
Synchronous CPU
Buck Controller for 12 V
and 5.0 V Applications
The CS51311 is a synchronous dual NFET Buck Regulator
Controller. It is designed to power the core logic of the latest high
performance CPUs. It uses the V2™ control method to achieve the
fastest possible transient response and best overall regulation. It
incorporates many additional features required to ensure the proper
operation and protection of the CPU and Power system. The CS51311
provides the industry’s most highly integrated solution, minimizing
external component count, total solution size, and cost.
The CS51311 is specifically designed to power Intel’s Pentium® II
processor and includes the following features: 5−bit DAC with 1.2%
tolerance, Power Good output, overcurrent hiccup mode protection,
VCC monitor, soft start, adaptive voltage positioning, adaptive FET
non−overlap time, and remote sense. The CS51311 will operate over
an 8.4 V to 14 V range and is available in 14 lead narrow body surface
mount package.
Features
• Synchronous Switching Regulator Controller for CPU VCORE
• Dual N−Channel MOSFET Synchronous Buck Design
• V2 Control Topology
• 200 ns Transient Loop Response
• 5−Bit DAC with 1.2% Tolerance
• Hiccup Mode Overcurrent Protection
• 40 ns Gate Rise and Fall Times (3.3 nF Load)
• 65 ns Adaptive FET Non−Overlap Time
• Adaptive Voltage Positioning
• Power Good Output Monitors Regulator Output
• VCC Monitor Provides Undervoltage Lockout
• Enable Through Use of the COMP Pin
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14
1
SO−14
D SUFFIX
CASE 751A
MARKING DIAGRAM
14
CS51311
AWLYWW
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
1
VID0
VID1
VID2
VID3
VID4
VFB
VOUT
14
COMP
COFF
PWRGD
GATE(L)
GND
GATE(H)
VCC
ORDERING INFORMATION
Device
Package
Shipping
CS51311GD14
SO−14
55 Units/Rail
CS51311GDR14
SO−14 2500 Tape & Reel
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 3
1
Publication Order Number:
CS51311/D
1 page  
CS51311
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCC < 14 V;
2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.)
Characteristic
Test Conditions
Min Typ Max Unit
Power Good Output
PWRGD Sink Current
PWRGD Upper Threshold
VFB = 1.7 V, VPWRGD = 1.0 V
% of Nominal DAC Code
0.5 4.0 15 mA
5.0 8.5 12 %
PWRGD Lower Threshold
% of Nominal DAC Code
−12 −8.5 −5.0 %
PWRGD Output Low Voltage
General Electrical Specifications
VFB = 1.7 V, IPWRGD = 500 μA
− 0.2 0.3 V
VCC Monitor Start Threshold
VCC Monitor Stop Threshold
Hysteresis
Start−Stop
−
−
7.9 8.4 8.9 V
7.6 8.1 8.6 V
0.15 0.3 0.6 V
VCC Supply Current
No Load on GATE(H), GATE(L)
− 12 20 mA
PACKAGE PIN #
SO−14
1, 2, 3, 4, 5
6
7
8
9
10
11
12
13
14
PACKAGE PIN DESCRIPTION
PIN SYMBOL
VID0−VID4
VFB
VOUT
VCC
GATE(H)
GND
GATE(L)
PWRGD
COFF
COMP
FUNCTION
Voltage ID DAC inputs. These pins are internally pulled up to 5.65 V if left
open. VID4 selects the DAC range. When VID4 is high (logic one), the Error
Amp reference range is 2.125 V to 3.525 V with 100 mV increments. When
VID4 is low (logic zero), the Error Amp reference voltage is 1.325 V to 2.075 V
with 50 mV increments.
Error amp inverting input, PWM comparator non−inverting input, current limit
comparator non−inverting input, PWRGD comparator input.
Current limit comparator inverting input.
Input power supply pin for the internal circuitry. Decouple with filter capacitor to
GND.
High side switch FET driver pin.
Ground pin.
Low side synchronous FET driver pin.
Power Good Output. Open collector output drives low when VFB is out of regu-
lation.
Off−Time Capacitor pin. A capacitor from this pin to GND sets the off time for
the regulator.
Error amp output. PWM comparator inverting input. A capacitor on this pin pro-
vides error amp compensation.
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5
5 Page 
CS51311
best Transient Response, a combination of a number of high
frequency and bulk output capacitors are usually used.
Slope Compensation
The V2 control method uses a ramp signal, generated by
the ESR of the output capacitors, that is proportional to the
ripple current through the inductor. To maintain regulation,
the V2 control loop monitors this ramp signal, through the
PWM comparator, and terminates the switch on−time.
The stringent load transient requirements of modern
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope presented to the PWM
comparator, due to the very low ESR, can lead to pulse width
jitter and variation caused by both random or synchronous
noise.
Adding slope compensation to the control loop, avoids
erratic operation of the PWM circuit, particularly at lower
duty cycles and higher frequencies, where there is not
enough ramp signal, and provides a more stable switchpoint.
The scheme that prevents that switching noise
prematurely triggers the PWM circuit consists of adding a
positive voltage slope to the output of the Error Amplifier
(COMP pin) during an off−time cycle.
The circuit that implements this function is shown in
Figure 13.
14
COMP
CCOMP
CS51311
R2
11
GATE(L)
C1
R1
To Synchronous FET
Figure 13. Small RC Filter Provides the
Proper Voltage Ramp at the Beginning of
Each On−Time Cycle
The ramp waveform is generated through a small RC filter
that provides the proper voltage ramp at the beginning of
each on−time cycle. The resistors R1 and R2 in the circuit of
Figure 13 form a voltage divider from the GATE(L) output,
superimposing a small artificial ramp on the output of the
error amplifier. It is important that the series combination
R1/R2 is high enough in resistance not to load down and
negatively affect the slew rate on the GATE(L) pin.
PROTECTION AND MONITORING FEATURES
Overcurrent Protection
A loss−less hiccup mode current limit protection feature
is provided, requiring only the COMP capacitor to
implement. The CS51311 provides overcurrent protection
by sensing the current through a “Droop” resistor, using an
internal current sense comparator. The comparator
compares the voltage drop through the “Droop” resistor to
an internal reference voltage of 86 mV (typical).
If the voltage drop across the “Droop” resistor exceeds
this threshold, the current sense comparator allows the fault
latch to be set. This causes the regulator to stop switching.
During this overcurrent condition, the CS51311 stays off
for the time it takes the COMP pin capacitor to discharge to
its lower 0.25 V threshold. As soon as the COMP pin reaches
0.25 V, the Fault latch is reset (no overcurrent condition
present) and the COMP pin is charged with a 30 μA current
source to a voltage 1.1 V greater than the VFB voltage. Only
at this point the regulator attempts to restart normally by
delivering short gate pulses to both FETS. The CS51311 will
operate initially with a duty cycle whose value depends on
how low the VFB voltage was during the overcurrent
condition (whether hiccup mode was due to excessive
current or hard short). This protection scheme minimizes
thermal stress to the regulator components, input power
supply, and PC board traces, as the overcurrent condition
persists. Upon removal of the overload, the fault latch is
cleared, allowing normal operation to resume.
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
normal operation of the V2 control topology and requires no
additional external components. The control loop responds
to an overvoltage condition within 200 ns, causing the top
MOSFET to shut off, disconnecting the regulator from its
input voltage. This results in a “crowbar” action to clamp the
output voltage and prevents damage to the load. The
regulator will remain in this state until the overvoltage
condition ceases or the input voltage is pulled low. The
bottom FET and board trace must be properly designed to
implement the OVP function.
Power Good Circuit
The Power Good pin (pin 12) is an open−collector signal
consistent with TTL DC specifications. It is externally
pulled up, and is pulled low (below 0.3 V) when the
regulator output voltage typically exceeds ±8.5% of the
nominal output voltage. Maximum output voltage deviation
before Power Good is pulled low is ±12%.
Output Enable
On/off control of the regulator outputs can be
implemented by pulling the COMP pins low. It is required
to pull the COMP pins below the 1.1 V PWM comparator
offset voltage in order to disable switching on the GATE
drivers.
CS51311−BASED VCC(CORE) BUCK REGULATOR
DESIGN PROCEDURE
Step 1: Definition of the Design Specifications
In computer motherboard applications the input voltage
comes from the “silver box” power supply. 5.0 V ± 5.0% is
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11
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CS51311.PDF ] | |
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