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PDF CS51414 Data sheet ( Hoja de datos )
| Número de pieza | CS51414 | |
| Descripción | (CS51411 - CS51414) Low Voltage Buck Regulators | |
| Fabricantes | ON Semiconductor | |
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CS51411, CS51412,
CS51413, CS51414
1.5 A, 260 kHz and 520 kHz,
Low Voltage Buck
Regulators with External
Bias or Synchronization
Capability
The CS5141X products are 1.5 A buck regulator ICs. These devices
are fixed−frequency operating at 260 kHz and 520 kHz. The regulators
use the V2™ control architecture to provide unmatched transient
response, the best overall regulation and the simplest loop
compensation for today’s high−speed logic. These products
accommodate input voltages from 4.5 V to 40 V.
The CS51411 and CS51413 contain synchronization circuitry. The
CS51412 and CS51414 have the option of powering the controller
from an external 3.3 V to 6.0 V supply in order to improve efficiency,
especially in high input voltage, light load conditions.
The on−chip NPN transistor is capable of providing a minimum of
1.5 A of output current, and is biased by an external “boost” capacitor
to ensure saturation, thus minimizing on−chip power dissipation.
Protection circuitry includes thermal shutdown, cycle−by−cycle
current limiting and frequency foldback. The CS51411 and CS51413
are functionally pin−compatible with the LT1375. The CS51412 and
CS51414 are functionally pin−compatible with the LT1376.
Features
• V2 Architecture Provides Ultrafast Transient Response, Improved
Regulation and Simplified Design
• 2.0% Error Amp Reference Voltage Tolerance
• Switch Frequency Decrease of 4:1 in Short Circuit Conditions
Reduces Short Circuit Power Dissipation
• BOOST Pin Allows “Bootstrapped” Operation to Maximize
Efficiency
• Sync Function for Parallel Supply Operation or Noise Minimization
• Shutdown Lead Provides Power−Down Option
• 85 mA Quiescent Current During Power−Down
• Thermal Shutdown
• Soft−Start
• Pin−Compatible with LT1375 and LT1376
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
MARKING DIAGRAMS
8
1
SOIC−8
D SUFFIX
CASE 751
8
5141x
ALYWy
G
1
18
1
18−LEAD DFN
MN SUFFIX
CASE 505
1 18
CS5141xy
AWLYYWW G
G
5141x = Device Code
x = 1, 2, 3 or 4
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
y = E or G
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 21
1
Publication Order Number:
CS51411/D
1 page  
CS51411, CS51412, CS51413, CS51414
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 125°C (CS51411E/2E/3E/4E); −40°C < TA < 85°C (CS51411E/2E/3E/4E);
0°C < TA < 70°C (CS51411G/2G/3G/4G), 4.5 V< VIN < 40 V; unless otherwise specified.)
Characteristic
Test Conditions
Min Typ Max
Sync
Sync Frequency Range
Sync Frequency Range
Sync Pin Bias Current
Sync Threshold Voltage
CS51411/CS51412
CS51413/CS51414
VSYNC = 0 V
VSYNC = 5.0 V
−
305 − 470
575 − 880
− 0.1 0.2
250 360 460
1.0 1.5 1.9
Shutdown
Shutdown Threshold Voltage
Shutdown Pin Bias Current
Thermal Shutdown
ICC = 2 mA
VSHDNB = 0 V
Overtemperature Trip Point
(Note 5)
Thermal Shutdown Hysteresis
(Note 5)
General
Quiescent Current
Shutdown Quiescent Current
Boost Operating Current
Minimum Boost Voltage
ISW = 0 A
VSHDNB = 0 V
VBOOST − VSW = 2.5 V
(Note 5)
Startup Voltage
−
Minimum Output Current
−
5. Guaranteed by design, not 100% tested in production.
1.0 1.3
0.14 5.00
175 185
− 42
−−
− 20
6.0 15
−−
2.2 3.3
− 7.0
1.6
35
195
−
6.25
85
40
2.5
4.4
12
Unit
kHz
kHz
mA
mA
V
V
mA
°C
°C
mA
mA
mA/A
V
V
mA
http://onsemi.com
5
5 Page 
CS51411, CS51412, CS51413, CS51414
VIN
SHDNB
(a)
(b)
I1
5mA
Q2
To internal
bias rails
20k Q1
D1
8V
0.65V
SHDNB
Z1
2V to 5V
(c)
SHDNB
where:
VC = VC pin steady−state voltage, which is approximately
equal to error amplifier’s reference voltage.
CCOMP = Compensation capacitor connected to the VC pin
ISOURCE = Output Source Current of the error amplifier.
Using a 0.1 mF CCOMP, the calculation shows a TSS over
5.0 ms which is adequate to avoid any current stresses.
Figure 16 shows the gradual rise of the VC, VO and envelope
of the VSW during power up. There is no voltage overshoot
after the output voltage reaches the regulation. If the supply
voltage rises slower than the VC pin, output voltage may
overshoot.
Figure 15. SHDNB pin equivalent internal circuit (a)
and practical interface examples (b), (c).
Figure 15(a) depicts the SHDNB pin equivalent internal
circuit. If the pin is open, current source I1 flows into the
base of Q1, turning both Q1 and Q2 on. In turn, Q2 collector
current enables the various internal power rails. In
Figure 15(b), a standard logic gate is used to pull the pin low
by shunting I1 to ground, which places the IC in sleep
(shutdown) mode. Note that, when the gate output is logical
high, the voltage at the SHDNB pin will rise to the internal
clamp voltage of 8 V. This level exceeds the maximum
output rating for most common logic families. Protection
Zener diode Z1 permits the pin voltage to rise high enough
to enable the IC, but remain less than the gate output voltage
rating. In Figure 15(c), a single open-collector general-
purpose NPN transistor is used to pull the pin low. Since
transistors generally have a maximum collector voltage
rating in excess of 8 V, the protection Zener diode in
Figure 15(b) is not required.
Startup
During power up, the regulator tends to quickly charge up
the output capacitors to reach voltage regulation. This gives
rise to an excessive in−rush current which can be detrimental
to the inductor, IC and catch diode. In V2 control, the
compensation capacitor provides Soft−Start with no need
for extra pin or circuitry. During the power up, the Output
Source Current of the error amplifier charges the
compensation capacitor which forces VC pin and thus output
voltage ramp up gradually.
The Soft−Start duration can be calculated by
TSS
+
VC CCOMP
ISOURCE
Figure 16. The Power Up Transition of CS5141X
Regulator
Short Circuit
When the VFB pin voltage drops below Foldback
Threshold, the regulator reduces the peak current limit by
40% and switching frequency to 1/4 of the nominal
frequency. These features are designed to protect the IC and
external components during overload or short circuit
conditions. In those conditions, peak switching current is
clamped to the current limit threshold. The reduced
switching frequency significantly increases the ripple
current, and thus lowers the DC current. The short circuit can
cause the minimum duty cycle to be limited by Minimum
Output Pulse Width. The foldback frequency reduces the
minimum duty cycle by extending the switching cycle. This
protects the IC from overheating, and also limits the power
that can be transferred to the output. The current limit
foldback effectively reduces the current stress on the
inductor and diode. When the output is shorted, the DC
current of the inductor and diode can approach the current
limit threshold. Therefore, reducing the current limit by 40%
can result in an equal percentage drop of the inductor and
diode current. The short circuit waveforms are captured in
http://onsemi.com
11
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CS51414.PDF ] | |
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