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PDF CS5954AM Data sheet ( Hoja de datos )
| Número de pieza | CS5954AM | |
| Descripción | USB Controller | |
| Fabricantes | Cypress Semiconductor | |
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ADVANCE
INFORMATION
CS5954AM
CS5954AM
USB Controller for NAND Flash
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-08025 Rev. **
Revised May 28, 2002
1 page  
ADVANCE
INFORMATION
CS5954AM
1.0 Definitions
USB
Universal Serial Bus
CS5954
The CS5954AM is a Cypress USB Controller, which provides multiple functions on a single chip.
QT Quick stream data Transfer engine, which contains a small set of RISC instructions designed for the
CS5954AM USB controller.
QTU
“QT” is a naming convention that represents QT Engine utility tools. For example: “QTU” indicates all
tools that interface with the USB port.
R/W Read/Write
PLL Phase Lock Loop
WDT
Watchdog Timer
RAM
Random Access Memory
2-wire serial interface 2-wire serial EEPROM interface
R0-R15
CS5954AM Registers
R0-R7 data registers or general-purpose registers
R8-R14 address/data registers, or general-purpose registers
R15 stack pointer register
CS5954AM BIOS
A simulation model similar to 80×86 BIOS
2.0 References
[Ref. 1] SL11R_BIOS
[Ref. 2] SL11R Family Tools
[Ref. 3] Universal Serial Bus Specification 2.0
3.0 Introduction
3.1 Overview
The CS5954AM is a low-cost, full-speed Universal Serial Bus (USB) RISC-based controller specifically designed for mass storage
applications using NAND Flash technology. It contains a 16-bit RISC processor with built-in BIOS ROM to greatly reduce firmware
development work. Its 2-wire serial EEPROM interface offers low cost storage for USB device configuration and customer’s
product-specific functions. New functions can be programmed into the 2-wire serial interface by downloading them from a USB
Host PC. This unique architecture provides the ability to upgrade products in the field without changing the peripheral hardware.
The CS5954AM Processor can execute code from either internal ROM/RAM or external ROM and SRAM. The CS5954AM
Programmable bidirectional data port supports I/O mode. A built-in USB port supports data transfers up to 12 MBits/sec which is
the maximum full speed USB transfer rate. All USB protocol modes are supported: Isochronous (up to 1024 bytes/packet), Bulk,
Interrupt, and Control. The CS5954AM requires a 3.3V power supply, which can be powered via a USB host PC or a Hub.
Suspend/Resume, and Low power modes are available.
The CS5954AM offers a cost effective solution for NAND Flash products.
3.2 Features
• Cypress offers a development kit for each of its product lines. These development kits include multiple peripheral
mini-port class drivers for Microsoft Windows 98/ME/2000, firmware source code and demo USB source code for
a variety of applications. Also available is a debugger and assembler with a reference demo board.
• 48-MHz 16-bit RISC processor.
• Up to 16 bits of programmable bidirectional data I/O.
• Up to 32 bits of general-purpose I/O (GPIO).
• 6K × 8 internal mask ROM with built-in BIOS supporting a comprehensive list of interrupt calls (see [Ref. 1] SL11R_BIOS
for detailed information). These include USB functions, 2-wire serial interface boot-up option (boot-up from 2-wire
serial interface or external ROM). Executable code can also run from 8-bit or 16-bit external memory.
• 3K × 8 internal RAM that can be configured as the USB Ping-Pong buffer for USB DATA0 and DATA1 packets. It can
also be used for data and/or code.
• Two-wire serial EEPROM interface port with CS5954AM BIOS support to allow on-board EEPROM programming.
• Flexible programmable external memory wait-states and a 8/16 data path.
• Up to 16-bit address for extended memory interface port for external SRAM and ROM.
Document #: 38-08025 Rev. **
Page 5 of 44
5 Page 
ADVANCE
INFORMATION
CS5954AM
4.5.2 USB Frame Number Register (0xC082: Read-only)
The Frame Number Register contains the 11-bit ID number of the last SOF received by the device from the USB host.[5]
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
D15-D11
D10-D0
Reserved
S10-S0
set to all zeros.
SOF ID number of last SOF received.
4.5.3 USB Address Register (0xC084: R/W)
Address Register holds the USB address of the device assigned by the Host–initialized to address 0x0000 upon power-up.[6]
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 A6 A5 A4 A3 A2 A1 A0
D15-D7
D6-D0
Reserved
A6-A0
set to all zeros.
USB address of device after assignment by host.
4.5.4 USB Command Done Register (0xC086: Write-only)
This is the USB Command Done Register. It is only used by the control point (endpoint 0).[7]
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
000000000000000E
D15–D1
Reserved
set to all zeros
D0 E
set E = 0 for successful command completion
set E = 1 for error command completion.
4.6 USB Endpoint 0 Control and Status Register (0xC090: R/W)
See the USB Endpoint 3 control and status register for more information.
4.7 USB Endpoint 1 Control and Status Register (0xC092: R/W)
See the USB Endpoint 3 control and status register for more information.
4.8 USB Endpoint 2 Control and Status Register (0xC094: R/W)
See the USB Endpoint 3 control and status register for more information.
4.9 USB Endpoint 3 Control and Status Register (0xC096: R/W)
4.9.1 General Description for All Endpoints from Endpoint 0 to Endpoint 3
The CS5954AM controller supports four endpoints. Endpoint 0 is the default pipe and is used to initialize and control the peripheral
device. It also provides access to the peripheral device’s configuration information, and supports control transfers. Endpoints 1,
2, and 3 support interrupt transfers, bulk transfers up to 64 Bytes/packet, or Isochronous transfers up to 1024 Bytes/packet size.
4.9.2 USB Endpoint Control (for Writing)
Each of the endpoint control registers, when written, have the following functions assigned.
Bit Position Bit Name
Function
D0
ARM
Allows enabled transfers when set to “1.” Cleared to “0” when transfer is complete.
D1 Enable When set to “1” it allows transfers to this endpoint. When set to “0” USB transactions are ignored.
If enable = “1” and Arm = “0” the endpoint will return NAK to USB transmissions.
D2 DIR When set to “1” it transmits to Host (IN). When “0” receive from Host (OUT).
D3 ISO When set to “1” it allows Isochronous mode for this endpoint.
D4 Stall When set to “1” it sends Stall in response to next request on this endpoint.
D5 Zero Length When set to “1” it sends a zero length packet.
D6–D15 Not Defined Set to logic “0”s.
Notes:
5. The CS5954AM BIOS uses this register to detect USB activity for the internal idle task.
6. The CS5954AM BIOS modifies this register upon receiving the SET_ADDRESS from the host. (See [Ref. 3] Universal Serial Bus Specification v2.0 sec. 9 for
more information.)
Document #: 38-08025 Rev. **
Page 11 of 44
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