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PDF DTA144TT1 Data sheet ( Hoja de datos )
| Número de pieza | DTA144TT1 | |
| Descripción | Bias Resistor Transistor PNP Silicon Surface Mount Transistor | |
| Fabricantes | ON Semiconductor | |
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DTA144TT1
Preferred Device
Bias Resistor Transistor
PNP Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base−emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the SC−59
package which is designed for low power surface mount applications.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Moisture Sensitivity Level: 1
• ESD Rating: Human Body Model: Class 1
Machine Model: Class B
• The SC−59 package can be soldered using wave or reflow.
The modified gull−winged leads absorb thermal stress during
soldering eliminating the possibility of damage to the die.
• Pb−Free Package is Available
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Symbol
Value
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
VCBO
VCEO
IC
50
50
100
THERMAL CHARACTERISTICS
Unit
Vdc
Vdc
mAdc
Characteristic
Total Device Dissipation
TA = 25°C
Derate above 25°C
Thermal Resistance,
Junction-to-Ambient
Thermal Resistance,
Junction-to-Lead
Junction and Storage Temperature
Range
Symbol
PD
RqJA
RqJL
TJ, Tstg
Max
230 (Note 1)
338 (Note 2)
1.8 (Note 1)
2.7 (Note 2)
540 (Note 1)
370 (Note 2)
264 (Note 1)
287 (Note 2)
−55 to +150
Unit
mW
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 x 1.0 inch Pad
http://onsemi.com
PNP SILICON BIAS
RESISTOR TRANSISTOR
R1
PIN 1 R2
BASE
(INPUT)
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
3
12
SC−59
CASE 318D
PLASTIC
MARKING DIAGRAM
6T M G
G
1
6T = Specific Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 3
1
Publication Order Number:
DTA144TT1/D
1 page | ||
| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet DTA144TT1.PDF ] | |
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