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부품번호 NJ88C50 기능
기능 Dual Low Power Frequency Synthesiser
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NJ88C50 데이터시트, 핀배열, 회로
www.DataSheet4U.com
NJ88C50
Dual Low Power Frequency Synthesiser
The NJ88C50 is a low power integrated circuit, designed
as the heart of a fast locking PLL subsystem in a mobile radio
application. It is manufactured on Mitel Semiconductor 1.4
micron double polysilicon CMOS process, which ensures that
low power and low noise performance is achieved. The device
contains two synthesisers, one for the generation of VHF
signals up to 125MHz and a second for UHF (when used with
a mulitmodulus prescaler such as the SP8713/14/15). The
main synthesiser has the capability of driving a dual speed
loop filter and also can perform Fractional-N interpolation.
Both synthesisers use current source outputs from their
phase detectors to minimise external components. Various
sections may be powered down for battery economy.
FEATURES
• 30MHz main synthesiser
• 125MHz auxiliary synthesiser
• Programmable output current
from phase detector - up to 10mA
• High input sensitivity
• Fractional-N interpolator
• Supports up to 4 modulus prescalers
• SSOP package
DS3805
ISSUE 1.8
Ordering Information
NJ88C50/MA/NP - (Industrial temp
range in SSOP package)
June 2002
AVDD
FIM
FIMB
DATA
CKIN
STROBE
RI
FIA
RSA
PDA
1 20
2 19
3 18
4 17
5 NJ88C50 16
6 15
7 14
8 13
9 12
10 11
AGND
MOD2
MOD1
SCREEN
RSC
RSM
VDD
PDP
GND
PDI
APPLICATIONS
• NMT, AMPS, ETACS cellular
• GSM, IS-54, RCR-27 cellular
• DCS1800 microcellular
• DLMR, DSRR, TETRA
• DECT, PHP cordless telephones
NP20
Figure 1 - Pin assignment
ABSOLUTE MAXIMUM RATINGS
Storage temperature
-55°C to +150°C
Operating temperature
-40°C to +85°C
Supply voltage
-0.5 to 7.0V
Voltage on any pin
-0.3V to (VDD + 0.3V)
FIM
FIMB
DATA
CKIN
STROBE
RI
FIA
MOD1
MOD2
MAIN N
BUFFER
SERIAL
INPUT
REGISTER
R BUFFER
AUX. N
BUFFER
MAIN N-DIVIDER
LATCH
LATCH
R DIVIDER
QBAR
Q
LATCH
AUX. N-DIVIDER
PHASE
DETECTOR
RSC RSM
CURRENT
SOURCE
PDI
PDP
LATCH
FRACTIONAL-N
SYSTEM
PHASE
DETECTOR
CURRENT
SOURCE
PDA
Figure 2 - Simplified block diagram
RSA




NJ88C50 pdf, 반도체, 판매, 대치품
NJ88C50
The main N divider is programmable so that it can
determine how many cycles of each division ratio the external
prescaler will perform.
The total division ratio of the output from the system VCO
to the synthesiser's phase detector may be expressed as NTOT
and R1, R2, R3 and R4 are the available prescaler ratios and
N1, N2, N3 and N4 are the corresponding number of cycles for
each ratio selected, within one complete division cycle.
The divider is programmed via the serial data bus and the
values needed to be programmed for each of the possible
prescaler ratios are as follows:-
In 2 modulus mode (division ratios R1, R2)
NTOT = N1.R1 + N2.R2
Programmed values needed:
N1 - a 12 bit value giving the number of times R1 is to be used
N2 - a 8 bit value giving the number of times R2 is to be used
In 3 modulus mode (division ratios R1, R2, R3)
NTOT = N1.R1 + N2.R2 + N3.R3
Programmed values needed:
N1 - a 12 bit value giving the number of times R1 is to be used
N2 - a 4 bit value giving the number of times R2 is to be used
N2+N3 - a 4 bit value where N3 is the number of times R3 is
to be used and (N2+N3) is modulo-16 addition
In 4 modulus mode (division ratios R1, R2, R3, R4)
NTOT = N1.R1 + N2.R2 + N3.R3 + N4.R4
Programmed values needed:
N1 - a 12 bit value giving the number of times R1 is to be used
N2 - a 4 bit value giving the number of times R2 is to be used
N2+N3 - a 4 bit value where N3 is the number of times R3 is
to be used.
N2+N3+N4 - a 4 bit value where N4 is the number of times R4
is to be used. (N2+N3) and (N2+N3+N4) are modulo-16
addition.
To facilitate the use of multimodulus prescalers the N
divider is based upon a twelve bit up/down counter which
functions as follows
The first value, N1, is loaded into the counter which then
counts down from N1 to zero. During this time, the modulus
ratio R1 is selected.
When the counter reaches zero modulus R2 is selected
and the counter then counts up to the N2 value. If 2 modulus
operation is chosen, the counter is then reloaded with N1 and
the count is repeated.
For operation with 3 or 4 modulus devices, the counter
continues to count up once it has reached the N2 value. The
count continues to the N2+N3 value and during this time the
R3 ratio is selected. In the 3 modulus case, when the N2+N3
value is reached the counter is then reloaded with the N1
value and the modulus ratio R1 is selected.
For 4 modulus operation the counter will continue its count
up to the N2+N3+N4 value before reloading the N1 value.
During this time the R4 modulus is selected.
If N2, N3, or N4 are set to zero this will give a full count of 16
for the corresponding modulus.
The N divider block also has a special control line from the
Fractional-N logic. When required this control will cause the
total division ratio to be increased from N to N+1. This is
achieved by forcing a cycle which would have normally used
a prescaler ratio R1 to use ratio R2 instead. R1 and R2 are
chosen so that R2 equals R1+1.
Further explanation of the operation of the synthesiser
when using 2, 3 or 4 modulus prescaler is given in the section
on multimodulus division (page 8).
The phase detector used on the main synthesiser is
similar to the type used on the auxiliary synthesiser (Figure.3).
In this case, however, the detector will drive two pairs of
complimentary charge pumps, one of which is intended to
drive the loop integrator capacitor to provide integral control,
whilst the other provides proportional control for the VCO.
This system is shown in Fig 5, and has applications where fast
locking of the loop is required.
Vdd Vdd
PROPORTIONAL
CHARGE
PUMP
TO VCO
INTEGRAL
CHARGE
PUMP
Gnd
Figure 5 - Loop filter using both charge pumps
Modes of Operation
Normal Mode
The synthesiser will operate in normal mode while the
strobe line of the serial data bus is low. In this mode the
following current levels are produced. The charge pump
providing the proportional feedback term will have a normal
current level designated by Iprop(0), that is set by an external
bias resistor, RSM. Iprop(0) will vary when different N-divider
ratios are programmed, so that it is proportional to the total
division ratio. To avoid the necessity of computing the total
division ratio on chip, an eight bit number representing the
most significant bits of Ntot will be loaded via the serial data
bus. Iprop(0) is therefore given by
Iprop(0) = CN.Ibo
where CN is the loaded eight bit number and the value Ibo is
scaled from the external current setting resistor RSM where
Ibo = Irsm/32. Typically Ibo = 1µA ,and therefore Iprop(0) will
have a maximum value equal to 255µA.
4

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NJ88C50 전자부품, 판매, 대치품
NJ88C50
MULTIMODULUS DIVISION
The NJ88C50 supports the use of 2, 3 and 4 modulus
prescalers. Two modulus prescalers such as the SP8714/15
are commonly used in PLLs. Additional information on using
2 modulus prescalers can be found in application note AN132
in the GEC Plessey Semiconductors Personal
Communications handbook (May 1992).
When using a 2 modulus prescaler (R/R+1) the minimum
division ratio above which all channels can be synthesised is
given by
Minimum division ratio = R(R-1)
eg. for a 64/65 prescaler such as the SP8714/15
Minimum division ratio = 64(64-1) = 4032
When fractional-N operation is being used higher comparison
frequencies are used, which are obtained by using lower
division ratios. Use of a 3 or 4 modulus prescaler allows the
minimum division ratio to be lowered.
For a 3 modulus prescaler (R/R+1/R+A)
Minimum division ratio = R(R+A+1)+A
A
eg. for a 64/65/72 prescaler such as the SP8713
Minimum division ratio = 64(64+8+1)+8 = 1096
8
For a 4 modulus prescaler (R/R+1/R+A/R+B)
Minimum division ratio = R(A+B+R+1)+A+B
AB
eg. for a 64/65/68/80 prescaler
Minimum division ratio = 64(4+16+64+1)+4+16 = 852
4 16
An example of where three modulus division would be
implemented is given below.
The system in which the synthesiser is to operate has a lowest
carrier frequency of 900MHz and a channel spacing of 30kHz.
However due to the lock up time requirements fractional-N
operation is being used in its 8ths mode (see section on
fractional-N operation), giving a comparison frequency of
30kHz x 8 = 240kHz.
Therefore,
Minimum division ratio required = 900x106 = 3750
240x103
If a 64/65 prescaler is used not all the channels will be
selectable as the minimum required division ratio is less than
the minimum allowable division ratio (4032).
If a 64/65/72 prescaler is used all the channels will now be
selectable as the minimum required division ratio will now be
greater than the minimum allowable division ratio (1096).
SERIAL DATA BUS
The data needed to program the synthesiser is entered via
a high speed (10MBit/s) 3-wire bus, with serial data, serial
clock and strobe pins. The input data is partitioned so that
after initial programming the output frequency can be
changed by re-programming only 24 or 32 bits.The timing
diagram for the bus is given in Fig.7.
The data is programmed as either four twenty-four bit
words or three twenty-four bit words and one thirty-two bit
word. When initially programmed words A, B, C and D are
loaded, though if the auxiliary synthesiser is disabled C is not
needed. Following the initial programming the frequency can
be subsequently shifted in one of the following ways:
a) If a 2 or 3 ratio prescaler is being used and CN does
not need to be reprogrammed word A should be
loaded.
b If a 2 or 3 ratio prescaler is being used and CN does
need to be reprogrammed word A2 should be loaded.
In wide frequency band systems CN must be
reprogrammed for best performance every time the
frequency is changed.
c) If a four ratio prescaler is being used word A and word
B should be loaded
STROBE
CKIN
DATA
MSB
Data must be valid on positive edges of clock
Figure 7
A strobe pulse occurs at the end of each word and loads
the contents of the input shift register into the working
registers, except when word B is being loaded, in which case
the shift register contents are loaded into a temporary register
and then loaded into the working register when either word A
or A2 is loaded. The information is transferred on the rising
edge of the strobe pulse which should occur one half clock
period after the clock edge on which the MSB of a word is
shifted in.
If word A or word A2 is being loaded, when the strobe goes
high the main synthesiser will be put into speed-up mode. This
mode will be maintained while the strobe remains high. During
this time any pulses on the clock input will not affect the
function of the synthesiser.
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관련 데이터시트

부품번호상세설명 및 기능제조사
NJ88C50

Dual Low Power Frequency Synthesiser

Mitel Networks Corporation
Mitel Networks Corporation
NJ88C50

Dual Low Power Frequency Synthesiser

Zarlink Semiconductor
Zarlink Semiconductor

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