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MC74VHC259 데이터시트 PDF




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부품번호 MC74VHC259 기능
기능 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter
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MC74VHC259 데이터시트, 핀배열, 회로
MC74VHC259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74VHC259 is an 8–bit Addressable Latch fabricated with
silicon gate CMOS technology. It achieves high speed operation similar to
equivalent Bipolar Schottky TTL devices while maintaining CMOS low
power dissipation.
The VHC259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in the
mode selection table.. In the addressable latch mode, the data on Data In
is written into the addressed latch. The addressed latch follows the data
input with all non–addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state and are
unaffected by the Data or Address inputs. In the one–of–eight decoding
or demultiplexing mode, the addressed output follows the state of Data In
with all other outputs in the LOW state. In the Reset mode, all outputs are
LOW and unaffected by the address and data inputs. When operating the
VHC259 as an addressable latch, changing more than one bit of the
address could impose a transient wrong address. Therefore, this should
only be done while in the memory mode.
The MC74VHC259 input structure provides protectionwwwwh.DeantaSvheoetl4tUa.cgomes
up to 7 V are applied, regardless of the supply voltage. This allows the
MC74VHC259 to be used to interface 5 V circuits to 3 V circuits.
High Speed: tPD = 7.6 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 2 µA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
CMOS–Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V
A0 1
A1 2
A2 3
Q0 4
Q1 5
Q2 6
Q3 7
GND 8
16 VCC
15 RESET
14 ENABLE
13 DATA IN
12 Q7
11 Q6
10 Q5
9 Q4
Figure 1. Pin Assignment
http://onsemi.com
MARKING DIAGRAMS
SOIC–16
D SUFFIX
CASE 751B
16 9
VHC259
AWLYYWW
18
TSSOP–16
DT SUFFIX
CASE 948F
SOIC EIAJ–16
M SUFFIX
CASE 966
16 9
VHC259
AWLYWW
1
8
16 9
VHC259
ALYW
18
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC74VHC259D
SOIC–16 48 Units/Rail
MC74VHC259DR2 SOIC–16 2500 Units/Reel
MC74VHC259DT TSSOP–16 96 Units/Rail
MC74VHC259DTR2 TSSOP–16 2500 Units/Reel
MC74VHC259M
SOIC
EIAJ–16
50 Units/Rail
SOIC
MC74VHC259MEL EIAJ–16 2000 Units/Reel
© Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 2
1
Publication Order Number:
MC74VHC259/D




MC74VHC259 pdf, 반도체, 판매, 대치품
MC74VHC259
MAXIMUM RATINGS (Note 1.)
Symbol
Parameter
Value
Unit
VCC
VIN
VOUT
IIK
IOK
IOUT
ICC
PD
Positive DC Supply Voltage
Digital Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air
SOIC Package
TSSOP
–0.5 to +7.0
–0.5 to +7.0
–0.5 to VCC +0.5
–20
$20
$25
$75
200
180
V
V
V
mA
mA
mA
mA
mW
TSTG
VESD
Storage Temperature Range
ESD Withstand Voltage
Human Body Model (Note 2.)
Machine Model (Note 3.)
Charged Device Model (Note 4.)
–65 to +150
>2000
>200
>2000
°C
V
ILATCH–UP
qJA
Latch–Up Performance
Above VCC and Below GND at 125°C (Note 5.)
Thermal Resistance, Junction to Ambient
SOIC Package
TSSOP
$300
143
164
mA
°C/W
1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
2. Tested to EIA/JESD22–A114–A
3. Tested to EIA/JESD22–A115–A
4. Tested to JESD22–C101–A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
VCC
VIN
VOUT
TA
tr, tf
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature Range, all Package Types
Input Rise or Fall Time
VCC = 3.3 V + 0.3 V
VCC = 5.0 V + 0.5 V
Min
2.0
0
0
–55
0
Max
5.5
5.5
VCC
125
20
Unit
V
V
V
°C
ns/V
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
80
90
100
110
120
130
140
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
1
1 10
100 1000
TIME, YEARS
Figure 5. Failure Rate vs. Time Junction Temperature
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MC74VHC259 전자부품, 판매, 대치품
MC74VHC259
PACKAGE DIMENSIONS
–A–
16
1
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
9
–B– P 8 PL
8 0.25 (0.010) M B S
G
–T– SEATING
PLANE
K
C
D 16 PL
0.25 (0.010) M T B S A S
R X 45_
F
MJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
0.15 (0.006) T U S
16
2X L/2
L
PIN 1
IDENT.
1
0.15 (0.006) T U S
0.10 (0.004)
–T– SEATING
PLANE
D
C
16X K REF
0.10 (0.004) M T U S V S
A
–V–
G
9
B
–U– J
8
N
N
K
K1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ÇÇÉÉÇÇÉÉÇÇJ1
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
SECTION N–N
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
0.25 (0.010)
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
M MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
F
DETAIL E
H DETAIL E
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C --- 1.20 --- 0.047
D 0.05 0.15 0.002 0.006
–W–
F
G
0.50 0.75 0.020 0.030
0.65 BSC
0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
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