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PDF MC74VHCT08A Data sheet ( Hoja de datos )
| Número de pieza | MC74VHCT08A | |
| Descripción | Quad 2-Input AND Gate | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74VHCT08A
Quad 2−Input AND Gate
The MC74VHCT08A is an advanced high speed CMOS 2−input
AND gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT08A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
• High Speed: tPD = 4.3 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
• TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
• Power Down Protection Provided on Inputs
www.DataSheet4U.com
• Balanced Propagation Delays
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: VOLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
• Chip Complexity: 24 FETs or 6 Equivalent Gates
• Pb−Free Packages are Available*
http://onsemi.com
MARKING
DIAGRAMS
14
SOIC−14
VHCT08AG
1
D SUFFIX
CASE 751A
AWLYWW
1
14
TSSOP−14
DT SUFFIX
1 CASE 948G
VHCT
08A
ALYWG
G
1
14
SOEIAJ−14
M SUFFIX
1 CASE 965
VHCT08
ALYWG
1
A = Assembly Location
WL, L = Wafer Lot
Y, YY = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 5
1
Publication Order Number:
MC74VHCT08A/D
1 page  
MC74VHCT08A
PACKAGE DIMENSIONS
−A−
14
1
G
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
8
−B− P 7 PL
7 0.25 (0.010) M B M
C R X 45 _
−T−
SEATING
PLANE
D 14 PL
K
0.25 (0.010) M T B S A S
M
F
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
0.15 (0.006) T U S
2X L/2 14
L
PIN 1
IDENT.
1
TSSOP−14
CASE 948G−01
ISSUE A
14X K REF
0.10 (0.004) M T U S V S
N 0.25 (0.010)
8
M
B
−U− N
F
7 DETAIL E
0.15 (0.006) T U S
A
−V−
K
ÇÇÇÉÉÇÇÇÉÉÇÇÇÉÉJ J1
K1
SECTION N−N
0.10 (0.004)
−T− SEATING
PLANE
D
C
G
H DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
−W−
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
http://onsemi.com
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