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부품번호 MC74VHCT139A 기능
기능 Dual 2-to-4 Decoder/ Demultiplexer
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MC74VHCT139A 데이터시트, 핀배열, 회로
MC74VHCT139A
Dual 2−to−4 Decoder/
Demultiplexer
The MC74VHCT139A is an advanced high speed CMOS 2−to−4
decoder/demultiplexer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL devices while maintaining CMOS low power
dissipation.
When the device is enabled (E = low), it can be used for gating or as
a data input for demultiplexing operations. When the enable input is
held high, all four outputs are fixed high, independent of other inputs.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device output is compatible with TTL−type input thresholds
and the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0 V CMOS logic to 5.0 V CMOS logic, or from 1.8 V CMOS logic
to 3.0 V CMOS logic while operating at the high−voltage power
supply
The MC74VHCT139A input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHCT139A to be used to interface 5.0 V circuits to
3.0 V circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help pwrwewv.DeatnaSthedet4eUv.ciocme
destruction caused by supply voltage−input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
High Speed: tPD = 5.0 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4 mΑ (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 100 FETs or 25 Equivalent Gates
Pb−Free Packages are Available*
http://onsemi.com
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
VHCT139AG
AWLYWW
11
16
TSSOP−16
VHCT
DT SUFFIX
139A
CASE 948F
ALYWG
G
11
16
SOEIAJ−16
M SUFFIX
CASE 966
74VHCT139
ALYWG
11
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
E A1 A0
H XX
L LL
L LH
L HL
L HH
Outputs
Y0 Y1 Y2 Y3
H HH H
L HH H
H LH H
H HL H
H HH L
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 4
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
MC74VHCT139A/D




MC74VHCT139A pdf, 반도체, 판매, 대치품
MC74VHCT139A
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC
TA = 25°C
TA 85°C TA = − 55 to
125°C
Symbol
VIH
Parameter
Minimum High−Level Input
Voltage
Condition
(V) Min Typ Max Min Max Min Max Unit
4.5 to 5.5 2
22 V
VIL Maximum Low−Level Input
Voltage
4.5 to 5.5
0.8 0.8 0.8 V
VOH Maximum High−Level
Output Voltage
VOL Maximum Low−Level
Output Voltage
IIN Input Leakage Current
ICC Maximum Quiescent
Supply Current
VIN = VIH or VIL
IOH = −50 mA
VIN = VIH or VIL
IOH = −8 mA
VIN = VIH or VIL
IOL = 50 mA
VIN = VIH or VIL
IOH = 8 mA
VIN = 5.5 V or GND
VIN = VCC or GND
4.5 4.4 4.5 4.4 4.4
V
4.5 3.94
3.8 3.66
V
4.5 0 0.1 0.1 0.1
4.5
0 to 5.5
5.5
0.36 0.44 0.52
±0.1 ±1.0 ±1.0 mA
4.0 40.0 40.0 mA
ICCT
Additional Quiescent
Supply Current (per Pin)
Any one input:
VIN = 3.4 V
All other inputs:
VIN = VCC or GND
5.5
1.35 1.5
1.5 mA
IOPD Output Leakage Current
VOUT = 5.5 V
0
0.5 5
5 mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (Input tr = tf= 3.0ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation
Delay, A to Y
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
tPHL
Maximum Propagation
Delay, E to Y
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCIN MaximumInput
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCapacitance
Test Conditions
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
VCC = 5.0 ± 0.5 V CL = 15 pF
CL = 50 pF
VCC = 3.3 ± 0.3 V CL = 15 pF
CL = 50 pF
VCC = 5.0 ± 0.5 V CL = 15 pF
CL = 50 pF
TA = 25°C
Min Typ Max
7.2 11.0
9.7 14.5
5.0 7.2
6.5 9.2
6.4 9.2
8.9 12.7
4.4 6.3
5.9 8.3
4 10
TA 85°C
Min Max
1.0 13.0
1.0 16.5
1.0 8.5
1.0 10.5
1.0 11.0
1.0 14.5
1.0 7.5
1.0 9.5
10
TA = − 55 to
125°C
Min Max
1.0 13.0
1.0 16.5
1.0 8.5
1.0 10.5
1.0 11.0
1.0 14.5
1.0 7.5
1.0 9.5
10
Unit
ns
ns
pF
Typical @ 25°C, VCC = 5.0V
CPD Power Dissipation Capacitance (Note 6)
26 pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC/2 (per decoder). CPD is used to determine the
no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.
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MC74VHCT139A 전자부품, 판매, 대치품
MC74VHCT139A
PACKAGE DIMENSIONS
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE A
0.15 (0.006) T U S
16
2X L/2
L
PIN 1
IDENT.
1
0.15 (0.006) T U S
0.10 (0.004)
−T− SEATING
PLANE
D
C
16X K REF
0.10 (0.004) M T U S V S
9
B
−U− J
8
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
K
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
J1 ÇÇÉÉÇÇÉÉK1ÇÇÉÉ
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
SECTION N−N
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
A
−V−
G
M
N
F
DETAIL E
H DETAIL E
−W−
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
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MC74VHCT139A/D

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MC74VHCT139A

Dual 2-to-4 Decoder/ Demultiplexer

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