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MC74VHCT259A 데이터시트 PDF




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부품번호 MC74VHCT259A 기능
기능 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter
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MC74VHCT259A 데이터시트, 핀배열, 회로
MC74VHCT259A
8−Bit Addressable
Latch/1−of−8 Decoder
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHCT259 is an 8−bit Addressable Latch fabricated with
silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The VHC259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in
the mode selection table. In the addressable latch mode, the signal on
Data In is written into the addressed latch. The addressed latch follows
the data input with all non−addressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous state and are unaffected by the Data or Address inputs. In the
one−of−eight decoding or demultiplexing mode, the addressed output
follows the state of Data In with all other outputs in the LOW state. In
the Reset mode, all outputs are LOW and unaffected by the address
and data inputs. When operating the VHCT259 as an addressable
latch, changing more than one bit of the address cowuwwld.DatiamShepeto4Us.ceoma
transient wrong address. Therefore, this should only be done while in
the memory mode.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V because it
has full 5.0 V CMOS level output swings.
The VHCT259A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage−input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
High Speed: tPD = 7.6 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V
Pb−Free Packages are Available*
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MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
VHCT259AG
AWLYWW
11
16
TSSOP−16
VHCT
DT SUFFIX
259A
CASE 948F
ALYWG
G
11
16
SOEIAJ−16
M SUFFIX
CASE 966
74VHCT259
ALYWG
11
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 4
1
Publication Order Number:
MC74VHCT259A/D




MC74VHCT259A pdf, 반도체, 판매, 대치품
MC74VHCT259A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
VIN
VOUT
IIK
IOK
IOUT
ICC
PD
Positive DC Supply Voltage
Digital Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air
Output in 3−State
High or Low State
SOIC Package
TSSOP
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−0.5 to VCC +0.5
−20
$20
$25
$75
200
180
V
V
V
mA
mA
mA
mA
mW
TSTG
VESD
Storage Temperature Range
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
−65 to +150
>2000
>200
>2000
°C
V
ILATCHUP
qJA
Latchup Performance
Above VCC and Below GND at 125°C (Note 4)
Thermal Resistance, Junction−to−Ambient
SOIC Package
TSSOP
$300
143
164
mA
°C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
VCC DC Supply Voltage
VIN DC Input Voltage
VOUT DC Output Voltage
TA Operating Temperature Range, all Package Types
tr, tf Input Rise or Fall Time
Output in 3−State
High or Low State
VCC = 5.0 V + 0.5 V
Min
4.5
0
0
0
−55
0
Max
5.5
5.5
5.5
VCC
125
20
Unit
V
V
V
°C
ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO
0.1% BOND FAILURES
Junction
Temperature °C
Time, Hours
Time, Years
80
1,032,200
117.8
90
419,300
47.9
100 178,700 20.4
110 79,600
9.4
120 37,000
4.2
130 17,800
2.0
140 8,900
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
1
1 10
100 1000
TIME, YEARS
Figure 5. Failure Rate vs. Time Junction Temperature
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MC74VHCT259A 전자부품, 판매, 대치품
MC74VHCT259A
ORDERING INFORMATION
Device
Package
Shipping
MC74VHCT259AD
SOIC−16
48 Units / Rail
MC74VHCT259ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74VHCT259ADR2
SOIC−16
2500 Tape & Reel
MC74VHCT259ADR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74VHCT259ADT
TSSOP−16*
96 Units / Rail
MC74VHCT259ADTG
TSSOP−16*
96 Units / Rail
MC74VHCT259ADTR2
TSSOP−16*
2500 Tape & Reel
MC74VHCT259ADTRG
TSSOP−16*
2500 Tape & Reel
MC74VHCT259AM
SOEIAJ−16
50 Units / Rail
MC74VHCT259AMG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC74VHCT259AMEL
SOEIAJ−16
2000 Tape & Reel
MC74VHCT259AMELG
SOEIAJ−16
(Pb−Free)
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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부품번호상세설명 및 기능제조사
MC74VHCT259A

8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter

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