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MC74VHCT373A 데이터시트 PDF




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부품번호 MC74VHCT373A 기능
기능 Octal D-Type Latch
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MC74VHCT373A 데이터시트, 핀배열, 회로
MC74VHCT373A
Octal D−Type Latch
with 3−State Output
The MC74VHCT373A is an advanced high speed CMOS octal latch
with 3−state output fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
This 8−bit D−type latch is controlled by a latch enable input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT373A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply
voltage−input/output voltage mismatch, battery backup, hot insertion,
etc.
Features
High Speed: tPD = 7.7 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°Cwww.DataSheet4U.com
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 4.5 V to 5.5 V Operating Range
Low Noise: VOLP = 1.6 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 196 FETs or 49 Equivalent Gates
Pb−Free Packages are Available*
http://onsemi.com
MARKING
DIAGRAMS
20
VHCT373A
1 SOIC−20WB
SUFFIX DW
AWLYYWWG
CASE 751D 1
20
1 TSSOP−20
SUFFIX DT
CASE 948E
1
VHCT
373A
ALYWG
G
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
INPUTS
OUTPUT
OE LE
D
Q
L HH
H
L HL
L
L L X No Change
HXX
Z
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 4
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Publication Order Number:
MC74VHCT373A/D




MC74VHCT373A pdf, 반도체, 판매, 대치품
MC74VHCT373A
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0V)
Symbol
Parameter
VOLP Quiet Output Maximum Dynamic VOL
VOLV Quiet Output Minimum Dynamic VOL
VIHD Minimum High Level Dynamic Input Voltage
VILD Maximum Low Level Dynamic Input Voltage
TA = 25°C
Typ Max
1.2 1.6
−1.2
−1.6
2.0
0.8
Unit
V
V
V
V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Symbol
Parameter
tw(h) Minimum Pulse Width, LE
tsu Minimum Setup Time, D to LE
th Minimum Hold Time, D to LE
Test Conditions
VCC = 5.0 ±0.5 V
VCC = 5.0 ± 0.5 V
VCC = 5.0 ± 0.5 V
TA = 25°C
Typ Limit
6.5
1.5
3.5
TA = − 40 to 85°C
Limit
8.5
1.5
3.5
Unit
ns
ns
ns
ORDERING INFORMATION
Device
MC74VHCT373ADWR2
Package
SOIC−20WB
Shipping
1000 / Tape & Reel
MC74VHCT373ADWRG
SOIC−20WB
(Pb−Free)
1000 / Tape & Reel
MC74VHCT373ADTR2
TSSOP−20*
2500 / Tape & Reel
MC74VHCT373ADTRG
TSSOP−20*
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
D
tPLH
Q
1.5V
1.5V
3V
GND
tPHL
VOH
VOL
Figure 3. Switching Waveform
tw
LE 1.5V
tPLH tPHL
3V
GND
Q 1.5V
VOH
VOL
Figure 4. Switching Waveform
OE 1.5V
tPZL tPLZ
Q 1.5V
tPZH tPHZ
Q 1.5V
3V
GND
HIGH
IMPEDANCE
VOL +0.3V
VOH −0.3V
HIGH
IMPEDANCE
Figure 5. Switching Waveform
VALID
D 1.5V
tsu th
LE 1.5V
3V
GND
3V
GND
Figure 6. Switching Waveform
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4

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MC74VHCT373A 전자부품, 판매, 대치품
MC74VHCT373A
PACKAGE DIMENSIONS
TSSOP−20
D5 SUFFIX
CASE 948E−02
ISSUE B
0.15 (0.006) T U S
2X L/2 20
L
PIN 1
IDENT
1
0.15 (0.006) T U S
C
D
0.100 (0.004)
−T− SEATING
PLANE
20X K REF
0.10 (0.004) M T U S V S
11
B
−U−
K
J JÍÍÍ1 ÍÍÍKÍÍÍ1 ÍÍÍ
SECTION N−N
10
N 0.25 (0.010)
AM
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
GH
N
F
DETAIL E
DETAIL E
−W−
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 6.40 6.60 0.252 0.260
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
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USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
7
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
MC74VHCT373A/D

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