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ZL50074 데이터시트 PDF




Zarlink Semiconductor에서 제조한 전자 부품 ZL50074은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 ZL50074 자료 제공

부품번호 ZL50074 기능
기능 32 K x 32 K Channel TDM Switch
제조업체 Zarlink Semiconductor
로고 Zarlink Semiconductor 로고


ZL50074 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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ZL50074 데이터시트, 핀배열, 회로
ZL50074
32 K x 32 K Channel TDM Switch
with 128 Input and 128 Output Streams
Data Sheet
Features
January 2006
• 32,768 channel x 32,768 channel non-blocking
digital Time Division Multiplex (TDM) switch at
65.536 Mbps, 32.768 Mbps or 16.384 Mbps
• 16,384 channel x 16,384 channel non-blocking
digital TDM switch at 8.192 Mbps
• Up to 128 serial TDM input streams, divided into
32 groups with 4 input streams per group
• Up to 128 serial TDM output streams, divided into
32 groups with 4 output streams per group
• Per-group input bit delay for flexible sampling
point selection
• Per-group output fractional bit advancement
• Four sets of output timing signals for interfacing
additional devices
• Per-channel constant or variable throughput
delay for frame integrity and low latency
applications
Ordering Information
ZL50074GAC 484 Ball LBGA Trays
ZL50074GAG2 484 Ball PBGA** Trays
**Pb Free Tin/Silver/Copper
-40°C to +85°C
• Control interface compatible with Intel and
Motorola Selectable 32 bit and 16 bit non-
multiplexed buses
• Connection Memory block programming
• Supports ST-BUS and GCI-Bus standards for
input and output timing
• IEEE 1149.1 (JTAG) test port
• 3.3 V I/O with 5 V tolerant inputs; 1.8 V core
Applications
• Per-channel high impedance output control
• Large Switching Platforms
• Per-channel force-high output control
• Per-channel message mode
• Centralwww.DataSheet4U.com Office Switches
• Wireless Base Stations and Controllers
• Multi-service Access Platforms
STiA0
STiB0
STiC0
STiD0
:
:
STiA31
STiB31
STiC31
STiD31
FPi2-0
CKi2-0
CK_SEL1-0
FPo3-0
CKo3-0
VDD_CORE VDD_IO VSS
ODE PWR
S/P
Converter
Input
Timing
Data Memory
P/S
Converter
Connection Memory
Output
Timing
Timing
Microprocessor Interface
and Control Registers
Test Access
Port
SToA0
SToB0
SToC0
SToD0
:
:
SToA31
SToB31
SToC31
SToD31
Figure 1 - ZL50074 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.




ZL50074 pdf, 반도체, 판매, 대치품
ZL50074
Data Sheet
List of Figures
Figure 1 - ZL50074 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Input Sampling Point Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3 - Output Bit Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6 - Read Cycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7 - Write Cycle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8 - Frame Pulse Input and Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 9 - Frame Skew Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 10 - ST-Bus Frame Pulse and Clock Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 11 - GCI Frame Pulse and Clock Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 12 - Serial Data Timing to CKi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 13 - Serial Data Timing to CKo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 14 - CKo to other CKo Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 15 - Microprocessor Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 16 - Intel Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 17 - JTAG Test Port & PWR Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4
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ZL50074 전자부품, 판매, 대치품
ZL50074
Data Sheet
Pin Diagram - ZL50074 23 mm x 23 mm 484 Ball PBGA (as viewed through top of package)
A1 corner identified by metallized marking
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A CKo STiA D[30] D[25] D[20] D[16] D[15] D[11] D[7] D[4] D[0] A[18] A[14] A[10] A[7] A[2] A[1] IC DTA PWR SToA TCK
[0] [0]
[31]
B
SToB STiD SToA D[31] D[26] D[21] D16B D[13] D[9]
[1] [1] [0]
D[5]
D[3] A[17] A[11] A[8]
A[6]
A[0] BERR SIZ[0] SToB STiA TDo STiA
[31] [31]
[30]
C
STiA STiA STiB STiD
[2] [3] [1] [0]
IM
D[27] D[22] D[19] D[12] D[6] D[1] A[15] A[9] A[3] R/W
CS
FPo STiD TRST SToD STiB STiD
[3] [31]
[30] [30] [29]
D
STiC STiD SToC SToD SToB STiC D[28] D[23] D[17] D[8] A[16] A[13] A[5]
[3] [2] [1] [0] [0] [0]
DS WAIT SToD STiB TDi SToB STiC SToA SToD
[31] [31]
[30] [30] [29] [28]
E
STiD SToB STiC SToA STiA SToC STiB D[24] D[18] D[14] D[2] A[12] A[4] CKo SIZ[1] STiC TMS SToC STiD SToD STiA STiB
[4] [3] [2] [1] [1] [0] [0]
[3] [31] [30] [30] [29] [29] [28]
F SToB SToC SToB SToD STiC
[4] [3] [2] [1] [1]
VSS
VDD_
CORE
D[29]
VDD_
IO
VDD_
CORE
D[10]
VDD_
IO
VDD_
CORE
SToC
[31]
VDD_
IO
VSS
VDD_
CORE
SToA
[30]
SToC
[29]
STiC
[29]
SToB
[28]
STiA
[28]
G SToD SToD SToD STiB
[4] [3] [2] [2]
FPo
[0]
VDD_
IO
VSS
VSS
VDD_ VDD_
CORE IO
VSS
VDD_ VDD_
CORE IO
VSS
VDD_ VDD_
CORE IO
VSS
SToB STiB STiC
[29] [29] [28]
CKi
[2]
STiD
[27]
H STiA
[5]
STiA
[4]
STiD
[3]
SToC
[2]
SToA
[2]
VDD_
CORE
VDD_
IO
VSS
VSS
VDD_ VDD_
CORE IO
VSS
VDD_ VDD_
CORE IO
VSS
VDD_
CORE
SToA
[28]
SToC
[28]
STiD
[28]
SToD
[27]
STiC
[27]
STiA
[27]
J STiB
[5]
CKi
[1]
STiC
[4]
SToA
[3]
STiB
[3]
VDD_
IO
VDD_
CORE
VDD_
IO
VSS
VSS
VSS
VSS
VSS
VSS
VDD_
IO
VSS
VDD_
IO
SToB
[27]
SToC
[27]
STiB
[27]
IC
SToC
[26]
K SToB STiD
[5] [5]
FPi
[1]
SToC SToA STiB
[4] [4] [4]
VSS
VDD_
CORE
VSS
VSS
VSS
VSS
VSS
VSS
VDD_
CORE
VDD_
IO
VDD_
CORE
SToA
[27]
FPi
[2]
SToA SToB STiD
[26] [26] [26]
L ODE
SToD SToC
[5] [5]
STiD
[6]
STiC
[5]
VDD_
CORE
VDD_
IO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD_
CORE
SToD
[26]
STiC
[26]
STiB
[26]
STiA SToD SToC
[26] [25] [25]
M STiA
[6]
STiB
[6]
STiC
[6]
STiC
[7]
SToA
[5]
VDD_
IO
VDD_
CORE
VDD_
IO
VSS
VSS
VSS
VSS
VSS
VSS
VDD_
IO
VSS
VDD_
IO
STiA
[25]
STiD
[25]
SToB SToA
[25] [25]
IC
N SToB SToC SToD SToA SToA
[6] [6] [6] [7] [6]
VSS
VSS VDD_ VSS
CORE
VSS
VSS
VSS
VSS
VSS
VDD_
CORE
VDD_
IO
SToD SToC
[23] [24]
STiD
[24]
SToB
[24]
STiB
[25]
STiC
[25]
P STiA
[7]
STiB
[7]
SToB
[7]
STiA
[8]
SToA
[8]
VDD_
CORE
VDD_
IO
VDD_
IO
VSS
VSS
VSS
VSS
VSS
VSS
VDD_
IO
VDD_
CORE
VDD_
CORE
SToA
[23]
STiC
[23]
STiB
[24]
SToA SToD
[24] [24]
R STiD SToC
[7] [7]
IC
SToB STiB
[8] [8]
VDD_ VDD_
IO CORE
VSS
VSS VDD_ VDD_ VSS VDD_ VDD_ VSS
CORE IO
CORE IO
VSS
VDD_
IO
CKo
[2]
STiD STiB
[22] [23]
STiA STiC
[24] [24]
T SToD
[7]
VSS
SToC STiD
[8] [9]
STiB SToD
[10] [9]
VSS
VSS VDD_ VDD_ VSS VDD_ VSS
CORE IO
CORE
VSS
VDD_ VDD_
CORE IO
VSS
SToA
[21]
FPo
[2]
SToC STiD SToC
[22] [23] [23]
U STiC SToD STiC
[8] [8] [9]
STiA SToC
[10] [10]
VSS
VDD_
IO
SToC
[12]
VDD_
IO
VDD_
CORE
STiA
[16]
VDD_
IO
VDD_
CORE
SToA
[18]
VDD_
IO
STiC
[19]
VDD_
CORE
SToC
[20]
STiD
[21]
STiC SToD SToB
[22] [22] [23]
V
STiD STiB SToC SToB SToD SToB STiC STiB SToA STiC SToB SToC
[8] [9] [9] [10] [10] [11] [12] [13] [13] [15] [16] [16]
IC CK_ STiB SToA STiA SToB SToD SToC SToA STiA
SEL[1] [18] [19] [20] [20] [20] [21] [22] [23]
W
STiA SToB STiD STiA SToA STiB SToD STiC STiA SToD SToC CKi
[9] [9] [10] [11] [11] [12] [12] [13] [14] [14] [15] [0]
IC SToB CK_ SToC STiD SToD STiD STiC STiA SToB
[17] SEL[0] [18] [19] [19] [20] [21] [22] [22]
Y SToA SToA STiB SToC SToA FPo STiD STiB SToB STiD SToD SToD IC STiC SToC STiA SToB STiB STiB SToA SToB STiB
[9] [10] [11] [11] [12] [1] [13] [14] [14] [15] [15] [16]
[17] [17] [18] [18] [19] [20] [20] [21] [22]
AA STiC STiC SToD STiD STiA SToB SToD SToA STiA SToA STiB SToA FPi STiA SToA IC
[10] [11] [11] [12] [13] [13] [13] [14] [15] [15] [16] [16] [0] [17] [17]
IC SToD SToB SToC STiA SToD
[18] [19] [19] [21] [21]
AB STiD STiA SToB CKo SToC STiC STiD SToC STiB SToB STiC STiD NC NC STiB STiD SToD STiC STiD STiA STiC STiB
[11] [12] [12] [1] [13] [14] [14] [14] [15] [15] [16] [16]
[17] [17] [17] [18] [18] [19] [20] [21]
7
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