PDF NB3N508S Data sheet ( Hoja de datos )

Número de pieza	NB3N508S
Descripción	PureEdge VCXO Clock Generator
Fabricantes	ON Semiconductor
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No Preview Available ! NB3N508S 3.3V, 216 MHz PureEdge VCXO Clock Generator with M−LVDS Output Description The NB3N508S is a high precision, low phase noise Voltage Controlled Crystal Oscillator (VCXO) and phase lock loop (PLL) that generates 216 MHz M−LVDS output from a 27 MHz crystal. The ±100 ppm output pullable range is obtained using the VIN pin of the VCXO with usable range from 0 V to 3.3 V. The VCXO input pin VIN is a high−impedance input that can be driven directly from a pulse width modulated RC integrator circuit. The NB3N508S is designed primarily for data and clock recovery applications within end products such as ADSL modems, set−top box receivers, and telecom systems. This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP−16 pin package. Features • PureEdge Clock Family Provides Accuracy and Precision • Performs Precision Clock Multiplication from 27 MHz Crystal • Uses 27 MHz Fundamental Mode Crystal • External Loop Filter is Not Required • 216 MHz M−LVDS Output • VCXO with Pull Range $100 ppm www.DataSheet4U.com • 0 V to 3.3 V VCXO Tuning Voltage Range Capabilities • Phase Noise: Offset 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz Noise Power −80 dBc −88 dBc −105 dBc −106 dBc −120 dBc −145 dBc • Operating Range 3.3 V $5% • These are Pb−Free Devices* http://onsemi.com 16 1 TSSOP−16 DT SUFFIX CASE 948F MARKING DIAGRAM 16 NB3N 508S ALYWG G 1 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 0 1 Publication Order Number: NB3N508S/D 1 page NB3N508S Table 5. AC CHARACTERISTICS (VDD = 3.135 V to 3.465 V, GND = 0 V, TA = 0°C to +70°C, Note 7) Symbol Characteristic Min Typ Max Unit fCLKIN fCLKOUT FNOISE Crystal Input Frequency Output Clock Frequency Phase−Noise Performance fCLKOUT = 216 MHz @ 100 Hz Offset from Carrier @ 1 kHz Offset from Carrier @ 10 kHz Offset from Carrier @ 100 kHz Offset from Carrier @ 1 MHz Offset from Carrier @ 10 MHz Offset from Carrier 27 216 −80 −88 −105 −106 −120 −145 MHz MHz dBc/Hz Spurious Noise Components −60 dBc/Hz FP tDUTY_CYCLE tR tF Crystal Pullability 0 V v VIN v 3.3 V Output Clock Duty Cycle (Measured at Crosspoint) Output Rise Time (CLK/CLK) (Note 8) Output Fall Time (CLK/CLK) (Note 8) "100 45 50 380 380 ppm 55 % 500 ps 500 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. CLK/CLK loaded with 50 W receiver termination resistor between diff. pair. 8. Measured differentially (CLK − CLK) at 10% to 90%; RL = 50 W. Phase Noise 10.00dB/Ref −20.00dBc/Hz OFFSET FREQUENCY (Hz) Figure 3. Typical Phase Noise Plot (VDD = 3.3 V, VIN = 0 V; Room Temperature) http://onsemi.com 5 5 Page

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