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부품번호 | NB4L52 기능 |
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기능 | Differential Data/Clock D Flip-Flop | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 8 페이지수
NB4L52
2.5 V/3.3 V/5.0 V Differential
Data/Clock D Flip-Flop
with Reset
Multi−Level Inputs to LVPECL Translator
w/ Internal Termination
The NB4L52 is a differential Data and Clock D flip−flop with a
differential asynchronous Reset. The differential inputs incorporate
internal 50 W termination resistors and will accept PECL, LVPECL,
LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock
transitions from Low to High, Data will be transferred to the
differential LVPECL outputs. The differential Clock inputs allow the
NB4L52 to also be used as a negative edge triggered device. The
device is housed in a small 3x3 mm 16 pin QFN package.
Features
• Maximum Input Clock Frequency > 4 GHz Typical
• 330 ps Typical Propagation Delay
• 145 ps Typical Rise and Fall Times
• Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical
• Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V
• Internal Input Termination Resistors, 50 W
• Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL,
LVEP, EP, and SG Devices
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
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1
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
1
NB4L
52
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD
D
D
VTD
VTCLK
CLK
CLK
VTCLK
Data
Clock
Reset
Q
Q
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 3
VTR R R VTR
Figure 1. Logic Diagram
Table 1. TRUTH TABLE
R D CLK
Hx
x
LL
LH
Z
Z
Z = LOW to HIGH Transition
x = Don’t Care
Q
L
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
1 Publication Order Number:
NB4L52/D
NB4L52
Table 5. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS
(VCC = 2.375 V to 5.5 V, VEE = 0 V or VCC = 0 V, VEE = −2.375 to −5.5 V, TA = −40°C to +85°C)
Symbol
Characteristic
Min Typ Max Unit
IEE Power Supply Current (Inputs and Outputs Open)
VOH
Output HIGH Voltage (Note 4, 5)
VCC = 5.0 V
VCC = 3.3 V
VCC = 2.5 V
VCC − 1145
3855
2155
1355
16
VCC − 1020
3980
2280
1480
25
VCC − 895
4105
2405
1605
mA
mV
VOL Output LOW Voltage (Note 4, 5)
VCC = 5.0V
VCC = 3.3V
VCC = 2.5V
VCC − 1945
3055
1355
555
VCC − 1770
3230
1530
730
VCC − 1600
3400
1700
900
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 4 & 7)
Vth Input Threshold Reference Voltage Range (Note 6)
VIH Single−ended Input HIGH Voltage
VIL Single−ended Input LOW Voltage
DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 5, 6 & 8 )
1050
Vth + 150
VEE
VCC − 150
VCC
Vth − 150
mV
mV
mV
VIHD
Differential Input HIGH Voltage
1200
VCC
mV
VILD
Differential Input LOW Voltage
VEE VCC − 150 mV
VCMR
Input Common Mode Range (Differential Configuration) (Note 7)
1125
VCC – 75
mV
VID Differential Input Voltage (VIHD − VILD)
150
VCC
mV
IIH Input HIGH Current D / D, CLK / CLK, R /R
(VTx/VTx Open)
−150
150 mA
IIL Input LOW Current D / D, CLK / CLK, R /R
(VTx/VTx Open)
−150
150 mA
RTIN
Internal Input Termination Resistor
40 50 60 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL outputs loaded with 50 W to VCC – 2.0 V for proper operation.
5. Input and output parameters vary 1:1 with VCC.
6. Vth is applied to the complementary input when operating in single−ended mode.
7. VCMRMIN varies 1:1 with VEE, VCMRMAX varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input
signal.
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4
4페이지 NB6L239
Driver
Device
Q
Q
NB4L52
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 10. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
Package
Shipping†
NB4L52MNG
QFN−16, 3 x 3 mm
(Pb−Free)
123 Units / Rail
NB4L52MNR2G
QFN−16, 3 x 3 mm
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPS I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
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7
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부품번호 | 상세설명 및 기능 | 제조사 |
NB4L52 | Differential Data/Clock D Flip-Flop | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |