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NB6N11S 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 NB6N11S은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 NB6N11S 자료 제공

부품번호 NB6N11S 기능
기능 Input to LVDS Fanout Buffer /Translator
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NB6N11S 데이터시트, 핀배열, 회로
NB6N11S
3.3 V 1:2 AnyLevelE Input
to LVDS Fanout Buffer /
Translator
Description
The NB6N11S is a differential 1:2 Clock or Data Receiver and will
accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL,
or LVDS. These signals will be translated to LVDS and two identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N11S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6N11S has a wide input common mode range from
GND + 50 mV to VCC 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6N11S is ideal for
translating a variety of differential or singleended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB6N11S is functionally equivalent to the EP11, LVEP11,
SG11 or 7L11M devices and is offered in a small, 3 mm X 3 mm,
16QFN package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB6N11S is a member of the ECLinPS MAXfamily of high
performance products.
Features
Maximum Input Clock Frequency > 2.0 GHz
www.DataSheet4U.com
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
These are PbFree Devices
http://onsemi.com
1
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6N
11S
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTD Q0
D
D
VTD
Figure 1. Logic Diagram
Q1
Q1
Device DDJ = 10 ps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2231 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
© Semiconductor Components Industries, LLC, 2006
May, 2006 Rev. 0
1
Publication Order Number:
NB6N11S/D




NB6N11S pdf, 반도체, 판매, 대치품
NB6N11S
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = 40°C to +85°C
Symbol
Characteristic
Min Typ Max Unit
ICC Power Supply Current (Note 8)
DIFFERENTIAL INPUTS DRIVEN SINGLEENDED (Figures 11, 12, 16, and 18)
35 50 mA
Vth Input Threshold Reference Voltage Range (Note 7)
VIH Singleended Input HIGH Voltage
VIL Singleended Input LOW Voltage
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8, 9, 10, 17, and 19)
GND +100
Vth + 100
GND
VCC 100
VCC
Vth 100
mV
mV
mV
VIHD
Differential Input HIGH Voltage
VILD
Differential Input LOW Voltage
VCMR Input Common Mode Range (Differential Configuration)
VID Differential Input Voltage (VIHD VILD)
RTIN
Internal Input Termination Resistor
LVDS OUTPUTS (Note 4)
100
VCC
mV
GND
VCC 100 mV
GND + 50
VCC 50 mV
100
VCC
mV
40 50 60 W
VOD Differential Output Voltage
250 450 mV
DVOD Change in Magnitude of VOD for Complementary Output States (Note 9)
0 1 25 mV
VOS Offset Voltage (Figure 15)
1125
1375
mV
DVOS Change in Magnitude of VOS for Complementary Output States (Note 9)
0 1 25 mV
VOH Output HIGH Voltage (Note 5)
1425
1600
mV
VOL Output LOW Voltage (Note 6)
900 1075
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 14.
5. VOHmax = VOSmax + ½ VODmax.
6. VOLmax = VOSmin ½ VODmax.
7. Vth is applied to the complementary input when operating in singleended mode.
8. Input termination pins open, D/D at the DC level within VCMR and output pins loaded with RL = 100 W across differential.
9. Parameter guaranteed by design verification not tested in production.
http://onsemi.com
4

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NB6N11S 전자부품, 판매, 대치품
NB6N11S
VCC
VCC
VCC
VCC
LVPECL
Driver
Zo = 50 W
VTD
VTD
Zo = 50 W
NB4N11S
D
50 W*
50 W*
D
GND
VTD = VTD = VCC 2.0 V
GND
Figure 7. LVPECL Interface
LVDS
Driver
Zo = 50 W
VTD
VTD
Zo = 50 W
VTD = VTD
NB4N11S
D
50 W*
50 W*
D
GND
GND
Figure 8. LVDS Interface
VCC
VCC
VCC
VCC
CML
Driver
GND
Zo = 50 W
VCC
VTD
VTD
Zo = 50 W
VTD = VTD = VCC
NB4N11S
D
50 W*
50 W*
D
GND
Figure 9. Standard 50 W Load CML Interface
VCC
VCC
HSTL
Driver
Zo = 50 W
VTD
VTD
Zo = 50 W
NB4N11S
D
50 W*
50 W*
D
GND
VTD = VTD = GND or VDD/2
Depending on Driver.
GND
Figure 10. HSTL Interface
VCC
VCC
LVCMOS
Driver
Zo = 50 W
VTD
VTD
NB4N11S
D
50 W*
50 W*
D
GND
GND
VTD = VTD = OPEN
D = GND
GND
Figure 11. LVCMOS Interface
*RTIN, Internal Input Termination Resistor.
http://onsemi.com
7
LVTTL
Driver
Zo = 50 W
VTD
VTD
NB4N11S
D
50 W*
50 W*
D
GND
GND
VTD = OPEN
D = GND
GND
Figure 12. LVTTL Interface

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부품번호상세설명 및 기능제조사
NB6N11S

Input to LVDS Fanout Buffer /Translator

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