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부품번호 | NB6N14S 기능 |
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기능 | Differential Input to LVDS Fanout Buffer/Translator | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 10 페이지수
NB6N14S
3.3 V 1:4 AnyLevelt
Differential Input to LVDS
Fanout Buffer/Translator
The NB6N14S is a differential 1:4 Clock or Data Receiver and will
accept AnyLevelt differential input signals: LVPECL, CML or
LVDS. These signals will be translated to LVDS and four identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N14S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6N14S has a wide input common mode range from
GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6N14S is ideal for
translating a variety of differential or single−ended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB6N14S is offered in a small 3 mm x 3 mm 16−QFN
package. Application notes, models, and support documentation are
available at www.onsemi.com.
The NB6N14S is a member of the ECLinPS MAXt family of high
performance products.
Features
• Maximum Input Clock Frequency > 2.0 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• 1 ps Maximum RMS Clock Jitter
www.DataSheet4U.com
• Typically 10 ps Data Dependent Jitter
• 380 ps Typical Propagation Delay
• 120 ps Typical Rise and Fall Times
• VREF_AC Reference Output
• TIA/EIA − 644 Compliant
• Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
• These are Pb−Free Devices
Device DDJ = 10 ps
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1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6N
14S
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
IN
VT
/IN
50 W
50 W
EN
(LVTTL/CMOS)
VREF_AC
DQ
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
© Semiconductor Components Industries, LLC, 2007
January, 2007 − Rev. 3
1
Publication Order Number:
NB6N14S/D
NB6N14S
Table 5. DC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
Symbol
Characteristic
Min Typ Max Unit
ICC Power Supply Current (Note 9)
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 10, 11, 15, and 17)
65 100 mA
Vth Input Threshold Reference Voltage Range (Note 8)
GND +100
VIH Single−ended Input HIGH Voltage
Vth + 100
VIL Single−ended Input LOW Voltage
GND
VREF_AC Reference Output Voltage (Note 11)
VCC − 1.600
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6, 7, 8, 9, 16, and 18)
VCC − 1.425
VCC − 100
VCC
Vth − 100
VCC − 1.300
mV
mV
mV
V
VIHD
Differential Input HIGH Voltage
VILD
Differential Input LOW Voltage
VCMR
Input Common Mode Range (Differential Configuration)
VID Differential Input Voltage (VIHD − VILD)
RTIN
Internal Input Termination Resistor
LVDS OUTPUTS (Note 5)
100
VCC
mV
GND
VCC − 100 mV
GND + 50
VCC − 50 mV
100
VCC
mV
40 50 60 W
VOD
DVOD
Differential Output Voltage
Change in Magnitude of VOD for Complementary Output States
(Note 10)
250 450 mV
0 1 25 mV
VOS
DVOS
Offset Voltage (Figure 14)
Change in Magnitude of VOS for Complementary Output States
(Note 10)
1125
1375
mV
0 1 25 mV
VOH Output HIGH Voltage (Note 6)
VOL Output LOW Voltage (Note 7)
LVTTL/LVCMOS INPUTS
1425
1600
mV
900 1075
mV
VIH Input HIGH Voltage (Note 7, 8)
2.0
VCC
V
VIL Input LOW Voltage (Note 7, 8)
GND
0.8 V
IIH Input HIGH Current
−150
150 mA
IIL Input LOW Current
−150
150 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 13.
6. VOHmax = VOSmax + ½ VODmax.
7. VOLmax = VOSmin − ½ VODmax.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. Input termination pins open, D/D at the DC level within VCMR and output pins loaded with RL = 100 W across differential.
10. Parameter guaranteed by design verification not tested in production.
11. VREF_AC used to rebias capacitor−coupled inputs only (see Figures 10 and 11).
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4
4페이지 NB6N14S
VCC
VCC
VCC
VCC
LVPECL
Driver
Zo = 50 W
VT = VCC − 2.0 V
Zo = 50 W
NB6N14S
CLK
50 W
50 W
CLK
VEE
VEE
Figure 6. LVPECL Interface
LVDS
Driver
Zo = 50 W
VT = OPEN
Zo = 50 W
NB6N14S
CLK
50 W
50 W
CLK
VEE
VEE
Figure 7. LVDS Interface
VCC
VCC
CML
Driver
Zo = 50 W
VT = VCC
Zo = 50 W
NB6N14S
CLK
50 W
50 W
CLK
VEE
VEE
Figure 8. Standard 50 W Load CML Interface
VCC
VCC
Differential
Driver
Zo = 50 W
VT = VREF_AC
Zo = 50 W
NB6N14S
CLK
50 W
50 W
CLK
VEE
VEE
Figure 10. Capacitor−Coupled Differential
Interface (VT Connected to VREF_AC)
VCC
VCC
HSTL
Driver
Zo = 50 W
VT =VEE
Zo = 50 W
NB6N14S
CLK
50 W
50 W
CLK
VEE
VEE
Figure 9. Standard 50 W Load HSTL Interface
VCC
VCC
Single−Ended
Driver
Zo = 50 W
VT = VREF_AC
NB6N14S
CLK
50 W
50 W
CLK
VEE
VEE
Figure 11. Capacitor−Coupled Single−Ended
Interface (VT Connected to VREF_AC)
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7
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부품번호 | 상세설명 및 기능 | 제조사 |
NB6N14S | Differential Input to LVDS Fanout Buffer/Translator | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |