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PDF NB6N239S Data sheet ( Hoja de datos )
| Número de pieza | NB6N239S | |
| Descripción | 3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT Clock Divider | |
| Fabricantes | ON Semiconductor | |
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NB6N239S
3.3 V, 3.0 GHz Any
Differential Clock IN to
LVDS OUT ÷1/2/4/8, ÷2/4/8/16
Clock Divider
Description
The NB6N239S is a high−speed, low skew clock divider with two
divider circuits, each having selectable clock divide ratios; B1/2/4/8
and B2/4/8/16. Both divider circuits drive LVDS compatible outputs.
(More device information on page 7). The NB6N239S is a member
of the ECLinPS MAX™ family of high performance clock products.
Features
• Maximum Clock Input Frequency, 3.0 GHz (1.5 GHz with B1)
• Input Compatibility with LVDS/LVPECL/CML/HSTL/HCSL
• Rise/Fall Time 120 ps Typical
• < 5 ps Typical Within Device Output Skew
• Example; 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz
Outputs
• Internal 50 W Termination Provided
• Random Clock Jitter < 2 ps RMS
• QA B1 Edge Aligned to QB Bn Edge
• Operating Range: VCC = 3.0 V to 3.465 V with GND = 0 V
• Master Reset for Synchronization of Multiple Chips
• VBBAC Reference Output
• Synchronous Output Enable/Disable
• TIA/EIA − 644 Compliant
• These Devices are Pb−Free and are RoHS Compliant
SELA0
SELA1
CLK
VT
CLK
VBBAC
50 W
50 W
EN
SELB0
SELB1
MR
+
B1
A
B2
B4
B8
R
B2
B4
B B8
B16
Figure 1. Simplified Logic Diagram
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1
Bottom View
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
1
NB6N
239S
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
QA
QA
QB
QB
© Semiconductor Components Industries, LLC, 2013
January, 2013 − Rev. 6
1
Publication Order Number:
NB6N239S/D
1 page  
NB6N239S
Table 7. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS
(VCC = 3.0 V to 3.465 V, GND = 0 V)
−405C
255C
85°C
Symbol Characteristic
Min Typ Max
Min Typ Max
Min Typ Max Unit
ICC Power Supply Cur-
rent (Inputs and
Outputs OPEN)
35 45 55
mA
VOH
Output HIGH
Voltage (Notes 2)
1600
1600
1600
mV
VOL Output LOW
900
900
900 mV
Voltage (Notes 2)
VOD Differential Output
Voltage (Figure 21)
250
450 250
450 250
450 mV
DVOD
VOD Magnitude
Change
0
50 0
50 0
50 mV
VOS Offset Voltage
(Figure 21)
1125
1375
1125
1375
1125
1375
mV
DVOS
VOS Magnitude
Change
0
50 0
50 0
50 mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 7, 10)
Vth Input Threshold
100
Reference Voltage
(Note 3)
VCC − 100
100
VCC − 100
100
VCC − 100
mV
VIH Single−ended Input Vth + 100
HIGH Voltage
VCC
Vth + 100
VCC
Vth + 100
VCC
mV
VIL
Single−ended Input
GND
LOW Voltage
Vth − 100
GND
Vth − 100
GND
Vth − 100
mV
VBBAC
Output Voltage Ref-
erence @ 100 mA
(Note 6)
3.3 V
VCC =
VCC−1460
1840
VCC−
1330
1970
VCC−1200
2100
VCC−1460
1840
VCC−
1340
1960
VCC−1200
2100
VCC−1460
1840
VCC−
1350
1950
VCC−1200
2100
mV
DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 8, 9, 11) (Note 5)
VIHD
Differential Input
HIGH Voltage
100
VCC 100
VCC 100
VCC
mV
VILD
Differential Input
LOW Voltage
GND
VCC – 100
GND
VCC – 100
GND
VCC – 100
mV
VCMR
Input Common
Mode Range (Dif-
ferential Cross−
point Voltage)
(Note 4)
50
VCC – 50
50
VCC – 50
50
VCC – 50
mV
VID Differential Input
Voltage (VIHD(CLK)
− VILD(CLK)) and
(VIHD(CLK) −
VILD(CLK))
100
VCC − GND
100
VCC − GND
100
VCC − GND mV
RTIN
Internal Input Ter-
45
50
55
mination Resistor
45 50 55
45 50 55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Outputs loaded with 100 W across LVDS outputs.
3. Vth is applied to the complementary input when operating in single−ended mode.
4. VCMRMIN varies 1:1 with GND, VCMRMAX varies 1:1 with VCC.
5. Input and output voltage swing is a single−ended measurement operating in differential mode.
6. VBBAC used to rebias capacitor−coupled inputs only (see Figures 16 and 17).
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5
5 Page 
NB6N239S
ORDERING INFORMATION
Device
Package
Shipping†
NB6N239SMNG
QFN−16, 3 x 3 mm
(Pb−Free)
123 Units / Rail
NB6N239SMNR2G
QFN−16, 3 x 3 mm
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
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11
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