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부품번호 | NB7L14M 기능 |
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기능 | Differential 1:4 Clock/Data Fanout Buffer/Translator | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 11 페이지수
NB7L14M
2.5V/3.3V Differential 1:4
Clock/Data Fanout Buffer/
Translator with CML
Outputs and Internal
Termination
Description
The NB7L14M is a differential 1−to−4 clock/data distribution chip
with internal source terminated CML output structures, optimized for
minimal skew and jitter. Device produces four identical output copies
of clock or data operating up to 8 GHz or 12 Gb/s, respectively. As
such, NB7L14M is ideal for SONET, GigE, Fiber Channel, Backplane
and other clock/data distribution applications.
Inputs incorporate internal 50 W termination resistors and accept
LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6).
Differential 16 mA CML outputs provide matching internal 50 W
terminations, and 400 mV output swings when externally terminated
with 50 W to VCC (See Figure 14).
The device is offered in a low profile 3x3 mm 16−pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
• Maximum Input Clock Frequency up to 8 GHz Typicalwww.DataSheet4U.com
• Maximum Input Data Rate up to 12 Gb/s Typical
• < 0.5 ps of RMS Clock Jitter
• < 10 ps of Data Dependent Jitter
• 30 ps Typical Rise and Fall Times
• 110 ps Typical Propagation Delay
• 6 ps Typical Within Device Skew
• Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
• CML Output Level (400 mV Peak−to−Peak Output) Differential
Output Only
• 50 W Internal Input and Output Termination Resistors
• Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
• Pb−Free Packages are Available
VTCLK
Q0
50 W
Q0
Q1
CLK Q1
CLK Q2
VTCLK
50 W
Figure 1. Logic Diagram
Q2
Q3
Q3
http://onsemi.com
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7L
14M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 1
1
Publication Order Number:
NB7L14M/D
NB7L14M
Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C)
(Note 5)
Symbol
Characteristic
Min Typ Max Unit
ICC Power Supply Current (Inputs and Outputs Open)
VOH Output HIGH Voltage (Note 6)
VOL Output LOW Voltage (Note 6)
Differential Input Driven Single−Ended (see Figures 10 & 12) (Note 8)
VCC − 60
VCC − 530
140
VCC − 20
VCC − 420
190
VCC
VCC − 360
mA
mV
mV
Vth Input Threshold Reference Voltage Range (Note 7)
VIH Single−ended Input HIGH Voltage (Note 8)
VIL Single−ended Input LOW Voltage (Note 8)
Differential Inputs Driven Differentially (see Figures 11 & 13) (Note 8)
1125
Vth + 75
VEE
VCC − 75
VCC
Vth − 75
mV
mV
mV
VIHCLK
VILCLK
VCMR
VID
IIH
IIL
RTIN
RTOUT
RTemp Coef
Differential Input HIGH Voltage
Differential Input LOW Voltage
Input Common Mode Range (Differential Configuration)
Differential Input Voltage (VIHCLK − VILCLK)
Input HIGH Current CLK / CLK (VTCLK/VTCLK Open)
Input LOW Current CLK / CLK (VTCLK/VTCLK Open)
Internal Input Termination Resistor
Internal Output Termination Resistor
Internal I/O Termination Resistor Temperature Coefficient
1200
VEE
1163
75
0
−10
45
45
25
0
50
50
6.38
VCC
VCC − 75
VCC – 38
2500
100
10
55
55
mV
mV
mV
mV
mA
mA
W
W
mW/°C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC.
6. CML outputs require 50 W receiver termination resistors to VCC for proper operation.
7. Vth is applied to the complementary input when operating in single−ended mode.
8. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC.
http://onsemi.com
4
4페이지 NB7L14M
NB7L14M
CLK
CLK
Q
Q
tPLH
VINPP = VIH(CLK) − VIL(CLK)
VOUTPP = VOH(Q) − VOL(Q)
tPHL
Figure 8. AC Reference Measurement
VCC
VCC
Receiver
Device
50 W
Q
Q
50 W
Z = 50 W
Z = 50 W
50 W
50 W
CLK
CLK
Figure 9. Typical Termination for 16 mA Output Driver and Device Evaluation
(Refer to Application Notes AND8020/D and AND8173/D)
CLK
Vth
Vth CLK
Figure 10. Differential Input Driven
Single−Ended
VCC
Vthmax
Vth CLK
Vthmin
GND
VIHmax
VILmax
VIH
Vth
VIL
VIHmin
VILmin
Figure 12. Vth Diagram
CLK
CLK
Figure 11. Differential Inputs Driven
Differentially
VCC
VCMmax
VCMR
CLK
CLK
VCMmax
GND
VIHCLKmax
VILCLKmax
V(CLK) = VIHCLK − VILCLK
VIHCLKtyp
VILCLKtyp
VIHCLKmin
VILCLKmin
Figure 13. VCMR Diagram
http://onsemi.com
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부품번호 | 상세설명 및 기능 | 제조사 |
NB7L14 | 2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer | ON Semiconductor |
NB7L14M | Differential 1:4 Clock/Data Fanout Buffer/Translator | ON Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |