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부품번호 NBC12439A 기능
기능 Programmable PLL Synthesized Clock Generator
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NBC12439A 데이터시트, 핀배열, 회로
NBC12439, NBC12439A
3.3V/5V Programmable PLL
Synthesized Clock
Generator
50 MHz to 800 MHz
Description
The NBC12439 and NBC12439A are general purpose, PLL based
synthesized clock sources. The VCO will operate over a frequency
range of 400 MHz to 800 MHz. The VCO frequency is sent to the
N--output divider, where it can be configured to provide division ratios
of 1, 2, 4 or 8. The VCO and output frequency can be programmed
using the parallel or serial interfaces to the configuration logic. Output
frequency steps of 16 MHz, 8 MHz, 4 MHz, or 2 MHz can be
achieved using a 16 MHz crystal, depending on the output divider
settings. The PLL loop filter is fully integrated and does not require
any external components.
Features
Best--in--Class Output Jitter Performance, ±20 ps Peak--to--Peak
50 MHz to 800 MHz Programmable Differential PECL Outputs
Fully Integrated Phase--Lock--Loop with Internal Loop Filter
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Parallel Interface for Programming Counter and Output Dividers
During Powerup
Minimal Frequency Overshoot
Serial 3--Wire Programming Interface
Crystal Oscillator Inputs 10 MHz to 20 MHz
Operating Range: VCC = 3.135 V to 5.25 V
CMOS and TTL Compatible Control Inputs
Pin and Function Compatible with Motorola MC12439 and
MPC9239
Powerdown of PECL Outputs (÷16)
0°C to 70°C Ambient Operating Temperature (NBC12439)
--40°C to 85°C Ambient Operating Temperature (NBC12439A)
Pb--Free Packages are Available
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MARKING
DIAGRAMS
1 28
PLCC--28
FN SUFFIX
CASE 776
NBC12439xG
AWLYYWW
LQFP--32
FA SUFFIX
CASE 873A
NBC12
439x
AWLYYWWG
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NBC12
439x
AWLYYWWG
G
x = Blank or A
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb--Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
February, 2007 -- Rev. 10
1
Publication Order Number:
NBC12439/D




NBC12439A pdf, 반도체, 판매, 대치품
NBC12439, NBC12439A
The following gives a brief description of the functionality of the NBC12439 and NBC12349A Inputs and Outputs. Unless
explicitly stated, all inputs are CMOS/TTL compatible with either pull--up or pulldown resistors. The PECL outputs are capable
of driving two series terminated 50 Ω transmission lines on the incident edge.
Table 3. PIN FUNCTION DESCRIPTION
Pin Name
INPUTS
XTAL1, XTAL2
Function
Crystal Inputs
S_LOAD*
CMOS/TTL Serial Latch Input
(Internal Pulldown Resistor)
S_DATA*
S_CLOCK*
P_LOAD**
CMOS/TTL Serial Data Input
(Internal Pulldown Resistor)
CMOS/TTL Serial Clock Input
(Internal Pulldown Resistor)
CMOS/TTL Parallel Latch Input
(Internal Pullup Resistor)
M[6:0]**
N[1:0]**
OE**
FREF_EXT*
CMOS/TTL PLL Loop Divider
Inputs (Internal Pullup Resistor)
CMOS/TTL Output Divider Inputs
(Internal Pullup Resistor)
CMOS/TTL Output Enable Input
(Internal Pullup Resistor)
CMOS/TTL Input
(Internal Pulldown Resistor)
Description
These pins form an oscillator when connected to an external series--resonant
crystal.
This pin loads the configuration latches with the contents of the shift registers. The
latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGH--to--LOW transition of S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.
This pin loads the configuration latches with the contents of the parallel inputs
.The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW--to--HIGH transition of P_LOAD for proper opera-
tion.
These pins are used to configure the PLL loop divider. They are sampled on the
LOW--to--HIGH transition of P_LOAD. M[6] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled
on the LOW--to--HIGH transition of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the FOUT output.
This pin can be used as the PLL Reference
XTAL_SEL**
CMOS/TTL Input
(Internal Pullup Resistor)
This pin selects between the crystal and the FREF_EXT source for the PLL refer-
ence signal. A HIGH selects the crystal input.
PWR_DOWN CMOS/TTL Input
(Internal Pulldown Resistor)
PWR_DOWN forces the FOUT outputs to synchronously reduce frequency by a
factor of 16.
OUTPUTS
FOUT, FOUT
PECL Differential Outputs
TEST
POWER
VCC
PLL_VCC
GND
CMOS/TTL Output
Positive Supply for the Logic
Positive Supply for the PLL
Negative Power Supply
-- Exposed Pad for QFN--32 only
* When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.
These differential, positive--referenced ECL signals (PECL) are the outputs of the
synthesizer.
The function of this output is determined by the serial configuration bits T[2:0].
The positive supply for the internal logic and output buffer of the chip, and is con-
nected to +3.3 V or +5.0 V.
This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
These pins are the negative supply for the chip and are normally all connected to
ground.
The Exposed Pad (EP) on the QFN--32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be at-
tached to a heat--sinking conduit. The pad is electrically connected to GND.
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NBC12439A 전자부품, 판매, 대치품
NBC12439, NBC12439A
Table 8. AC CHARACTERISTICS (VCC = 3.135 V to 5.25 V ± 5%; TA = 0°C to 70°C (NBC12439), TA = --40°C to 85°C
(NBC12439A)) (Note 7)
Symbol
Characteristic
Condition
Min Max Unit
FIN Input Frequency
S_CLOCK (Note 6)
Xtal Oscillator
FREF_EXT (Note 8)
-- 10 MHz
10 20
10 100
FOUT
tLOCK
tjitter(pd)
tjitter(cyc--cyc)
ts
Output Frequency
Maximum PLL Lock Time
Period Jitter (RMS)
VCO (Internal)
FOUT
(1σ)
Cycle--to--Cycle Jitter (Peak--to--Peak)
(8σ)
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
50 MHz fOUT < 100 MHz
100 MHz fOUT < 800 MHz
50 MHz fOUT < 100 MHz
100 MHz fOUT < 800 MHz
400
50
20
20
20
800
800
10
8
5
40
20
--
--
--
MHz
ms
ps
ps
ns
th Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20 -- ns
20 --
20 --
tpwMIN
Minimum Pulse Width
S_LOAD
P_LOAD
50 -- ns
50 --
DCO
Output Duty Cycle
47.5 52.5 %
tr, tf Output Rise/Fall
FOUT 20%--80%
175 425 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as
a test clock in TEST_MODE 6.
7. FOUT/FOUT outputs are terminated through a 50 Ω resistor to VCC -- 2.0 V. Internal phase detector can handle up to 100 MHz on it’s input.
8. Maximum frequency on FREF_EXT is a function of setting the appropriate M counter value, 20 M 80, for the VCO to operate within
the valid range of 400 MHz fVCO 800 MHz. (See Table 11)
9. See applications information section.
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