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부품번호 NBC12429A 기능
기능 Programmable PLL Synthesized Clock Generator
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NBC12429A 데이터시트, 핀배열, 회로
NBC12429, NBC12429A
3.3V/5V Programmable PLL
Synthesized Clock
Generator
25 MHz to 400 MHz
Description
The NBC12429 and NBC12429A are general purpose,
Phase--Lock--Loop (PLL) based synthesized clock sources. The VCO
will operate over a frequency range of 200 MHz to 400 MHz. The
VCO frequency is sent to the N--output divider, where it can be
configured to provide division ratios of 1, 2, 4, or 8. The VCO and
output frequency can be programmed using the parallel or serial
interfaces to the configuration logic. Output frequency steps of
125 kHz, 250 kHz, 500 kHz, or 1.0 MHz can be achieved using a
16 MHz crystal, depending on the output dividers. The PLL loop filter
is fully integrated and does not require any external components.
Features
Best--in--Class Output Jitter Performance, ±20 ps Peak--to--Peak
25 MHz to 400 MHz Programmable Differential PECL Outputs
Fully Integrated Phase--Lock--Loop with Internal Loop Filter
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Parallel Interface for Programming Counter and Output Dividers
During Powerup
Minimal Frequency Overshoot
Serial 3--Wire Programming Interface
Crystal Oscillator Interface
Operating Range: VCC = 3.135 V to 5.25 V
CMOS and TTL Compatible Control Inputs
Pin and Function Compatible with Motorola MC12429 and
MPC9229
0°C to 70°C Ambient Operating Temperature (NBC12429)
--40°C to 85°C Ambient Operating Temperature (NBC12429A)
Pb--Free Packages are Available
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MARKING
DIAGRAMS
1 28
PLCC--28
FN SUFFIX
CASE 776
NBC12429xG
AWLYYWW
LQFP--32
FA SUFFIX
CASE 873A
NBC12
429x
AWLYYWWG
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NBC12
429x
AWLYYWWG
G
x = Blank or A
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb--Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
February, 2007 -- Rev. 10
1
Publication Order Number:
NBC12429/D




NBC12429A pdf, 반도체, 판매, 대치품
NBC12429, NBC12429A
The following gives a brief description of the functionality of the NBC12429 and NBC12429A Inputs and Outputs. Unless
explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable
of driving two series terminated 50 Ω transmission lines on the incident edge.
Table 3. PIN FUNCTION DESCRIPTION
Pin Name
Function
INPUTS
XTAL1, XTAL2 Crystal Inputs
S_LOAD*
CMOS/TTL Serial Latch Input
(Internal Pulldown Resistor)
S_DATA*
S_CLOCK*
P_LOAD**
CMOS/TTL Serial Data Input
(Internal Pulldown Resistor)
CMOS/TTL Serial Clock Input
(Internal Pulldown Resistor)
CMOS/TTL Parallel Latch Input
(Internal Pullup Resistor)
M[8:0]**
N[1:0]**
OE**
OUTPUTS
FOUT, FOUT
TEST
POWER
VCC
PLL_VCC
GND
--
CMOS/TTL PLL Loop Divider
Inputs (Internal Pullup Resistor)
CMOS/TTL Output Divider Inputs
(Internal Pullup Resistor)
CMOS/TTL Output Enable Input
(Internal Pullup Resistor)
PECL Differential Outputs
CMOS/TTL Output
Positive Supply for the Logic
Positive Supply for the PLL
Negative Power Supply
Exposed Pad for QFN--32 only
* When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.
Description
These pins form an oscillator when connected to an external series--resonant
crystal.
This pin loads the configuration latches with the contents of the shift registers. The
latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGH--to--LOW transition of S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.
This pin loads the configuration latches with the contents of the parallel inputs.
The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW--to--HIGH transition of P_LOAD for proper opera-
tion.
These pins are used to configure the PLL loop divider. They are sampled on the
LOW--to--HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled
on the LOW--to--HIGH transition of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the FOUT output.
These differential, positive--referenced ECL signals (PECL) are the outputs of the
synthesizer.
The function of this output is determined by the serial configuration bits T[2:0].
The positive supply for the internal logic and output buffer of the chip, and is con-
nected to +3.3 V or +5.0 V.
This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
These pins are the negative supply for the chip and are normally all connected to
ground.
The Exposed Pad (EP) on the QFN--32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be at-
tached to a heat--sinking conduit. The pad is electrically connected to GND.
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NBC12429A 전자부품, 판매, 대치품
NBC12429, NBC12429A
Table 8. AC CHARACTERISTICS (VCC = 3.125 V to 5.25 V; TA = 0°C to 70°C (NBC12429), TA = --40°C to 85°C (NBC12429A))
(Note 6)
Symbol
Characteristic
Condition
Min Max Unit
FMAXI
Maximum Input Frequency
S_CLOCK (Note 7)
Xtal Oscillator
10 MHz
10 20
FMAXO
Maximum Output Frequency
VCO (Internal)
FOUT
200 400 MHz
25 400
tjitter(pd)
Period Jitter @ 3.3 V
10000 WFMS
(See Table 13 for Typical Values)
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
25 psRMS
9.0
6.0
9.0
5.0
4.0
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
146 psPP
71
53
125
60
54
Period Jitter @ 5.0 V
10000 WFMS
(See Table 13 for Typical Values)
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
25 psRMS
9.0
6.0
10
6.0
5.0
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
168 psPP
69
57
133
49
108
tjitter(cyc--cyc)
Cycle--to--Cycle @ 3.3 V
1000 WFMS
(See Table 13 for Typical Values)
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
20 psRMS
11
8.0
17
10
9.0
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
150 psPP
105
77
208
94
89
Cycle--to--Cycle @ 5.0 V
1000 WFMS
(See Table 13 for Typical Values)
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
25 psRMS
12
8.0
18
11
10
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
192 psPP
131
76
164
128
186
tLOCK
Maximum PLL Lock Time
10 ms
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
6. FOUT/FOUT outputs are terminated through a 50 Ω resistor to VCC -- 2.0 V.
7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used
as a test clock in TEST_MODE 6.
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