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WM8195 데이터시트 PDF




Wolfson Microelectronics에서 제조한 전자 부품 WM8195은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 WM8195 기능
기능 14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser
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WM8195 데이터시트, 핀배열, 회로
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WM8195
14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser
DESCRIPTION
FEATURES
The WM8195 is a 14-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 12MSPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset Adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is time multiplexed into a single high-speed 14-bit
analogue-to-digital converter. The digital output data is
available in 14-bit parallel or 8, 7 or 4-bit wide multiplexed
format, with no missing codes.
14-bit ADC
No missing codes guaranteed
12MSPS conversion rate
Low power – 210mW typical
5V single supply or 5V/3.3V dual supply operation
Single or 3 channel operation
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
14-bit parallel or 8, 7 or 4-bit wide multiplexed data output
formats
Internally generated voltage references
48-lead TQFP package
An internal 4-bit DAC is supplied for internal reference level
Serial or parallel control interface
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
APPLICATIONS
signals. Alternatively an external reference level may be
applied. ADC references are generated internally, ensuring
optimum performance from the device.
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
Using an analogue supply voltage of 5V and a digital
High-performance CCD sensor interface
interface supply of either 5V or 3.3V, the WM8195 typically
only consumes 210mW when operating from a single 5V
www.DataSheet4U.com
supply and less than 20µA when in power down mode.
BLOCK DIAGRAM
VRLC/VBIAS
CL
RINP
RLC
GINP
RLC
VSMP MCLK
AVDD1-2
DVDD1-3
RS VS
M
U
X
TIMING CONTROL
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WM8195
CDS
RM
GU
X
B
8
OFFSET
DAC
VREF/BIAS
+ PGA
RM
GU
X
B
I/P SIGNAL
8 POLARITY
ADJUST
CDS
+ PGA
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
VRT VRX VRB
+
M
+U
X
14-
BIT
ADC
DATA
I/O
PORT
BINP
RLC
RLC
DAC 4
CDS
+ PGA
+
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
CONFIGURABLE
SERIAL/
PARALLEL
CONTROL
INTERFACE
OEB
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
OP[8]
OP[9]
OP[10]
OP[11]
OP[12]
OP[13]/SDO
SEN/STB
SCK/RNW
SDI/DNA
RLC/ACYC
NRESET
AGND1-6
DGND1-5
WOLFSON MICROELECTRONICS plc
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Production Data July 2005 Rev 4.1
Copyright 2005 Wolfson Microelectronics plc.




WM8195 pdf, 반도체, 판매, 대치품
WM8195
Production Data
PIN DESCRIPTION
PIN NAME
TYPE
DESCRIPTION
1
VRX
Analogue output Input return bias voltage.
This pin must be decoupled to AGND via a capacitor.
2 VRLC/VBIAS Analogue I/O Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be decoupled to AGND via a capacitor.
VRLC can be externally driven if programmed Hi-Z.
3 AGND1
Supply
Analogue ground (0V).
4
BINP
Analogue input Blue channel input video.
5 AGND2
Supply
Analogue ground (0V).
6
GINP
Analogue input Green channel input video.
7 AGND3
Supply
Analogue ground (0V).
8
RINP
Analogue input Red channel input video.
9 AGND4
Supply
Analogue ground (0V).
10 DVDD1
Supply
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
11
OEB
Digital input Output Hi-Z control, all digital outputs disabled when OEB = 1.
12
SEN/STB
Digital input Serial interface: enable pulse, active high Parallel interface: strobe, active low
Latched on NRESET rising edge: if Low then device control is via serial interface,
if high then device control is via parallel interface.
13
SDI/DNA
Digital input Serial interface: serial input data signal
Parallel interface:
High = data, Low = address
14 SCK/RNW Digital input Serial interface: serial clock signal
Parallel interface:
High: OP[13:6] is output bus.
Low: OP[13:6] is input bus (Hi-Z).
15
VSMP
Digital input Video sample synchronisation pulse.
16 RLC/ACYC Digital input RLC (active high) selects reset level
ACYC autocycles between R, G, B
clamp on a pixel-by-pixel basis – tie high inputs when in Line-by-Line mode.
if used on every pixel.
17
MCLK
Digital input Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
18 DGND1
Supply
Digital ground (0V).
19 NC
No connection.
20 NC
No connection.
21
OP[0]
Digital output Pins OP[13:0] form a Hi-Z digital bi-directional bus. There are several modes:
22
OP[1]
Digital output Hi-Z: when OEB = 1.
23
OP[2]
Digital output 14-bit output: 14-bit data is output on OP[13:0].
8-bit multiplexed output: data is output on OP[13:6] at 2 ADC conversion rate.
7-bit multiplexed output: data is output on OP[13:6] at 2 ADC conversion rate.
4-bit multiplexed output: data is output on OP[13:10] at 4 ADC conversion rate.
See Output Formats section in Device Description for further details.
Input 8-bit: control data is input on OP[13:6] in parallel mode when SCK/RNW = 0,
and SEN/STB = 0.
Output 8-bit: register read back data is output in parallel on OP[13:6] when
SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1.
24 DVDD2
Supply
Digital I/O supply (3.3V/5V).
25 DGND2
Supply
Digital ground (0V).
26
OP[3]
Digital output See pins 21 to 23 for details.
27
OP[4]
Digital output
28
OP[5]
Digital output
29 OP[6]
Digital I/O
30 DGND3
Supply
Digital ground (0V).
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PD Rev 4.1 July 2005
4

4페이지










WM8195 전자부품, 판매, 대치품
Production Data
WM8195
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz unless
otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN TYP
Overall System Specification (including 14-bit ADC, PGA, Offset and CDS functions)
NO MISSING CODES GUARANTEED
Conversion rate
12
Full-scale input voltage range
(see Note 1)
Max Gain
Min Gain
0.4
4.08
Input signal limits (see Note 2)
VIN
0
Full-scale transition error
Gain = 0dB;
20
PGA[7:0] = 4B(hex)
Zero-scale transition error
Gain = 0dB;
PGA[7:0] = 4B(hex)
20
Differential non-linearity
DNL
1.25
Integral non-linearity
INL
8
Channel to channel gain matching
1
Total output noise
Min Gain
1
Max Gain
3
References
Upper reference voltage
VRT
2.85
Lower reference voltage
VRB
1.35
Input return bias voltage
VRX
1.65
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRTB
1.4 1.5
1
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
50
VRLC short-circuit current
5
VRLC output resistance
2
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
RLCDAC resolution
4
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
VRLCSTEP
VRLCSTEP
VRLCBOT
0.25
0.17
0.39
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
0.26
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
VRLCTOP
4.16
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLCTOP
2.81
VRLC deviation
-50
Offset DAC, Monotonicity Guaranteed
Resolution
8
Differential non-linearity
DNL
0.1
Integral non-linearity
INL
0.25
Step size
2.04
Output voltage
Code 00(hex)
-260
Code FF(hex)
+260
Notes:
1. Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain.
2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
MAX
UNIT
AVDD
MSPS
Vp-p
Vp-p
V
mV
mV
LSB
LSB
%
LSB rms
LSB rms
V
V
V
1.6 V
mA
1 µA
bits
V/step
V/step
V
V
V
V
+50 mV
bits
0.5 LSB
1 LSB
mV/step
mV
mV
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PD Rev 4.1 July 2005
7

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