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PDF WM8216 Data sheet ( Hoja de datos )

Número de pieza WM8216
Descripción 60MSPS 10-bit 2-channel CCD Digitiser
Fabricantes Wolfson Microelectronics 
Logotipo Wolfson Microelectronics Logotipo



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WM8216
60MSPS 10-bit 2-channel CCD Digitiser
DESCRIPTION
FEATURES
The WM8216 is a 10-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 60MSPS.
10-bit ADC
60MSPS conversion rate
Low power – 330mW typical
3.3V single supply operation
The device includes two analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset adjust functions. The output from each of these
channels is time multiplexed into a single high-speed 10-bit
Analogue to Digital Converter. The digital output data is
available in 10-bit wide parallel format.
Single or dual channel operation
Correlated double sampling
Programmable gain (9-bit resolution)
Programmable offset adjust (8-bit resolution)
Flexible clamp timing
Programmable clamp voltage
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
Internally generated voltage references
32-lead QFN package
signals or during Clamping to clamp CCD signals. An
Serial control interface
external reference level may also be supplied. ADC
references are generated internally, ensuring optimum
APPLICATIONS
performance from the device.
Using an analogue supply voltage of 3.3V and a digital
interface supply of 3.3V, the WM8216 typically only
consumes 330mW
Digital Copiers
USB2.0 compatible scanners
Multi-function peripherals
High-speed CCD/CIS sensor interface
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WOLFSON MICROELECTRONICS plc
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Production Data, March 2007, Rev 4.0
Copyright ©2007 Wolfson Microelectronics plc.

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WM8216 pdf
WM8216
Production Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN MAX
Analogue supply voltage: AVDD
GND - 0.3V
GND + 4.2V
Digital supply voltages: DVDD1 2
GND - 0.3V
GND + 4.2V
Digital ground: DGND
GND - 0.3V
GND + 0.3V
Analogue grounds: AGND1 2
GND - 0.3V
GND + 0.3V
Digital inputs, digital outputs and digital I/O pins
GND - 0.3V
DVDD2 + 0.3V
Analogue inputs (EINP, OINP)
GND - 0.3V
AVDD + 0.3V
Other pins
GND - 0.3V
AVDD + 0.3V
Operating temperature range: TA
Storage temperature prior to soldering
Storage temperature after soldering
0°C
-65°C
+70°C
30°C max / 85% RH max
+150°C
Notes:
1. GND denotes the voltage of any ground pin.
2. AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages
between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
Operating temperature range
TA 0
70 °C
Analogue supply voltage
AVDD
2.97
3.3
3.63
V
Digital core supply voltage
DVDD1
2.97
3.3
3.63
V
Digital I/O supply voltage
DVDD2
2.97
3.3
3.63
V
Notes:
1. DVDD2 should be operated at the same potential as DVDD1 ± 0.3V.
THERMAL PERFORMANCE
PARAMETER
Performance
Thermal resistance – junction to
case
Thermal resistance – junction to
ambient
SYMBOL TEST CONDITIONS
RθJC
RθJA
Tambient = 25°C
MIN
TYP
10.27
29.45
Notes:
1. Figures given are for package mounted on 4-layer FR4 according to JESD51-5 and JESD51-7.
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MAX
UNIT
°C/W
°C/W
PD Rev 4.0 March 2007
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WM8216 arduino
WM8216
Production Data
The powers supplies can be brought up in any order but is important that either AVDD is brought up
before DVDD or vice versa as shown in Figure 5 and Figure 6.
Figure 5 Typical Power up Sequence where AVDD is Powered before DVDD1
Figure 5 shows a typical power-up sequence where AVDD comes up first. When AVDD goes above
the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted
low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now
AVDD is at full supply level. Next DVDD1 rises to Vpord_on and PORB is released high and all
registers are in their default state and writes to the control interface may take place.
Note: It is recommended that every time power is cycled to the WM8216 a software reset is written
to the software register to ensure that the contents of the control registers are at their default values
before carrying out any other register writes.
On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the
minimum threshold Vpora_off.
Figure 6 Typical Power up Sequence where DVDD1 is Powered before AVDD
Figure 6 shows a typical power-up sequence where DVDD1 comes up first. First it is assumed that
DVDD1 is already up to specified operating voltage. When AVDD goes above the minimum
threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the
chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD rises
to Vpora_on, PORB is released high and all registers are in their default state and writes to the
control interface may take place.
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PD Rev 4.0 March 2007
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