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WM8581 데이터시트 PDF




Wolfson Microelectronics에서 제조한 전자 부품 WM8581은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 WM8581 자료 제공

부품번호 WM8581 기능
기능 Multichannel CODEC
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WM8581 데이터시트, 핀배열, 회로
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WM8581
Multichannel CODEC with S/PDIF Transceiver
DESCRIPTION
FEATURES
The WM8581 is a multi-channel audio CODEC with S/PDIF
transceiver. The WM8581 is ideal for DVD and surround
Multi-channel CODEC with 4 Stereo DACs and 1 Stereo
ADC
sound processing applications for home hi-fi, automotive
and other audiovisual equipment.
Integrated S/PDIF / IEC-60958-3 transceiver
Audio Performance
Integrated into the device is a stereo 24-bit multi-bit sigma
103dB SNR (‘A’ weighted @ 48kHz) DAC
delta ADC with support for digital audio output word lengths
from 16-bit to 32-bit, and sampling rates from 8kHz to
192kHz.
-90dB THD (48kHz) DAC
100dB SNR (‘A’ weighted @ 48kHz) ADC
-87dB THD (48kHz) ADC
Also included are four stereo 24-bit multi-bit sigma delta
DACs, each with a dedicated oversampling digital
interpolation filter. Digital audio input word lengths from 16-
bits to 32-bits and sampling rates from 8kHz to 192kHz are
supported. Each DAC channel has independent digital
volume and mute control.
Two independent audio data interfaces support I2S, Left
Justified, Right Justified and DSP digital audio formats.
Each audio interface can operate in either Master Mode or
Slave Mode.
DAC Sampling Frequency: 8kHz – 192kHz
ADC Sampling Frequency: 8kHz – 192kHz
Independent ADC and DAC Sample Rates
2 and 3-Wire Serial Control Interface with readback, or
Hardware Control Interface
GPO pins allow visibility of user selected status flags
Programmable Audio Data Interface Modes
I2S, Left, Right Justified or DSP
16/20/24/32 bit Word Lengths
The S/PDIF transceiver is IEC-60958-3 compatible
supports frame rates from 32k/s to 96k/s. It has
multiplexed inputs and one output. Status and
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DAC outputs with independent
or Slave Audio Data Interfaces
monitoring is built-in and results can reported over the serial
Flexible Digital Interface Routing with Clock Selection
interface or via GPO pins. S/PDIF Channel Block
Control
configuration is also supported.
The device has two PLLs that can be configured
independently to generate two system clocks for internal or
2.7V to 5.5V Analogue, 2.7V to 3.6V Digital Supply
Operation
48-lead TQFP Package
external use.
Device control and setup is via a 2-wire or 3-wire (SPI
compatible) serial interface. The serial interface provides
access to all features including channel selection, volume
controls, mutes, de-emphasis, S/PDIF control/status, and
power management facilities. Alternatively, the device has a
Hardware Control Mode where device features can be
enabled/disabled using selected pins.
APPLICATIONS
Digital TV
DVD Players and Receivers
Surround Sound AV Processors and Hi-Fi systems
Automotive Audio
The device is available in a 48-lead TQFP package.
WOLFSON MICROELECTRONICS plc
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Production Data, April 2007, Rev 4.0
Copyright ©2007 Wolfson Microelectronics plc




WM8581 pdf, 반도체, 판매, 대치품
WM8581
PIN CONFIGURATION
Production Data
ORDERING INFORMATION
DEVICE
WM8581AGEFT/V
TEMPERATURE
RANGE
-25 to +85oC
WM8581AGEFT/RV
Note:
Reel quantity = 2,200
-25 to +85oC
PACKAGE
48-lead TQFP
(Pb-free)
48-lead TQFP
(Pb-free, tape and reel)
MOISTURE
SENSITIVITY LEVEL
MSL1
PEAK
SOLDERING
TEMPERATURE
260°C
MSL1
260°C
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PD Rev 4.0 April 2007
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WM8581 전자부품, 판매, 대치품
Production Data
WM8581
PIN FUNCTION
TYPE
PAIFTX_BCLK
Digital Input/Output
ADCMCLK
Digital Input
SAIF_DIN
Digital Input
SAIF_DOUT
Digital Output
SAIF_BCLK
Digital Input/Output
SAIF_LRCLK
Digital Input/Output
SPDIFIN2/3/4
Digital Input
GPO1 - GPO7
Digital Output
DR1/2/3/4
Digital Input
ALLPD
Digital Input
Table 2 Multi-Function Pin Description
DESCRIPTION
Primary Audio Interface Transmitter (PAIFTX) Bit Clock
Master ADC clock; 256fs, 384fs, 512fs ,786fs, 1024fs or 1152fs
Secondary Audio Interface (SAIF) Receiver data input
Secondary Audio Interface (SAIF) Transmitter data output
Secondary Audio Interface (SAIF) Bit Clock
Secondary Audio Interface (SAIF) Left/Right Word Clock
S/PDIF Receiver Input
General Purpose Output
Internal Digital Routing Configuration in Hardware Mode
Chip Powerdown in Hardware Mode
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PD Rev 4.0 April 2007
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