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PDF WM8594 Data sheet ( Hoja de datos )
| Número de pieza | WM8594 | |
| Descripción | Multi-Channel CODEC | |
| Fabricantes | Wolfson Microelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de WM8594 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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WM8594
24-bit 192kHz 2Vrms Multi-Channel CODEC
DESCRIPTION
FEATURES
The WM8594 is a high performance multi-channel audio
CODEC with flexible input/output selection and digital and
• Multi-channel CODEC with 5 stereo input selector and 3
stereo output selector
analogue volume control. Features include a 24-bit stereo
• 4-channel DAC, 2-channel ADC
ADC with digital gain control, two 24-bit DACs with
independent digital volume control, and a range of
input/output channel selection options with analogue volume
control, for flexible routing within current and future audio
systems.
The WM8594 accepts five stereo audio inputs at line levels
up to 2Vrms. One stereo input can be routed to the ADC. All
inputs can be routed to the output.
The WM8594 outputs three stereo audio channels at line
levels up to 2Vrms, which can be selected from any of the
analogue inputs and DAC outputs. Additionally, one stereo
output is available with a headphone driver. The DAC
• Five stereo 2Vrms stereo inputs with analogue bypass to
three stereo 2Vrms outputs
• Stereo headphone driver
• Audio performance
- DAC: 100dB SNR typical (‘A’ weighted @ 48kHz)
- DAC: -90dB THD typical
- ADC: 100dB SNR typical (‘A’ weighted @ 48kHz)
- ADC: -90dB THD typical
• Independent sampling rates for ADC, DAC1 and DAC2
• DACs sampling frequency 32kHz to 192kHz
• ADC sampling frequency 32kHz to 96kHz
channels include independent digital volume control, and all
three stereo output channels include analogue volume
control with soft ramp.
• ADC digital gain control: +30dB to -97dB
• DAC digital volume control: +12dB to -100dB
• Analogue Volume control with soft ramp: +6dB to -73.5dB
The WM8594 supports up to 2Vrms analogue inputs, 2Vrms
• All volume controls include zero cross detection to prevent
outputs, with sampling rates from 32kHz to 192kHz for the
pops and clicks
DACs, and 32kHz to 96kHz for the ADC.
www.DataSheet4U.com
• 2 and 3-wire serial control interface with readback and
The WM8594 is ideal for audio applications requiring high
performance and flexible routing options, including flat panel
hardware reset, mute and powerdown pins
• Master or slave clocking modes
digital TV and DVD recorder.
• Programmable format audio data interface modes
The device is controlled via a serial interface with support
for 2-wire and 3-wire control with full readback. Control of
- I2S, LJ, RJ, DSP
• 3.3V / 9V analogue, 3.3V digital supply operation
mute, powerdown and reset can also be achieved by pin
selection.
• 48-lead TQFP package
The WM8594 is available in a 48-lead TQFP package.
APPLICATIONS
• Digital Flat Panel TV
• DVD-RW
WOLFSON MICROELECTRONICS plc
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Product Preview, January 2007, Rev 1.0
Copyright ©2007 Wolfson Microelectronics plc
1 page  
Product Preview
WM8594
PIN DESCRIPTION
PIN NAME
1 ADCLRC
2 ADCBCLK
3 DOUT
4 DACMCLK1
5 DACLRC1
6 DACBCLK1
7 DIN1
8 DACMCLK2
9 DACLRC2
10 DACBCLK2
11 DIN2
12 DVDD
13 DGND
14 /PWDN
15 MUTE
16 /RESET
17 AVDD2
18 AGND2
19 VOUT3R
20 VOUT3L
21 VOUT2R
22 VOUT2L
23 VOUT1R
24 VOUT1L
25 VIN1L
26 VIN1R
27 VIN2L
28 VIN2R
29 VIN3L
30 VIN3R
31 VIN4L
32 VIN4R
33 VIN5L
34 VIN5R
35 ADCREFP
36 ADCVMID
37 ADCREFN
38 DACREFP
39 DACVMID
40 DACREFN
41 AVDD1
42 AGND1
43 MODE
44 SDOUT
45 /CS
46 SCLK
47 SDIN
48 ADCMCLK
TYPE
Digital Input/Output
Digital Input/Output
Digital Output
Digital Input
Digital input
Digital Input
Digital Input
Digital Input
Digital input
Digital Input
Digital Input
Supply
Supply
Digital Input
Digital Input
Digital Input
Supply
Supply
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Output
Analogue Input
Analogue Input
Analogue Output
Analogue Input
Supply
Supply
Digital Input
Digital Output
Digital Input
Digital Input
Digital Input
Digital Input
DESCRIPTION
ADC audio interface left/right clock input/output
ADC audio interface bit clock input/output
ADC data output
DAC1 master clock
DAC1 audio interface left/right clock input
DAC1 audio interface bit clock input
DAC 1 data input
DAC2 master clock
DAC2 audio interface left/right clock input
DAC2 audio interface bit clock input
DAC 2 data input
Digital supply
Digital ground
Hardware standby mode
Hardware DAC mute
Hardware reset
Analogue 9V supply
Analogue ground
Output selector channel 3 right output
Output selector channel 3 left output
Output selector channel 2 right output
Output selector channel 2 left output
Output selector channel 1 right output
Output selector channel 1 left output
Input selector channel 1 left input
Input selector channel 1 right input
Input selector channel 2 left input
Input selector channel 2 right input
Input selector channel 3 left input
Input selector channel 3 right input
Input selector channel 4 left input
Input selector channel 4 right input
Input selector channel 5 left input
Input selector channel 5 right input
Positive reference for ADC
Midrail divider decoupling pin for ADC
Ground reference for ADC
Positive reference for DACs
Midrail divider decoupling pin for DACs
Ground reference for DACs
Analogue 3.3V supply
Analogue ground
Software mode select (High = 3-wire, Low = 2-wire)
Software mode: serial control interface data output
Software mode: serial control interface chip select
Software mode: serial control interface clock signal
Software mode: serial control interface data signal
ADC master clock input
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PP Rev 1.0 January 2007
5
5 Page 
Product Preview
MASTER CLOCK TIMING
ADCMCLK/
DACMCLK1/
DACMCLK2
Figure 1 MCLK Timing
t
MCLKY
Test Conditions
AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25OC
PARAMETER
SYMBOL
MIN
Master Clock Timing Information
MCLK System clock cycle time
MCLK Duty cycle
tMCLKY
27
40:60
MCLK Period Jitter
MCLK Rise/Fall times
Table 1 Master Clock Timing Requirements
WM8594
TYP
MAX
UNIT
120
60:40
200
10
ns
%
ps
ns
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PP Rev 1.0 January 2007
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WM8594.PDF ] | |
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