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PDF NB100LVEP224 Data sheet ( Hoja de datos )
| Número de pieza | NB100LVEP224 | |
| Descripción | 1:24 Differential ECL/PECL Clock Driver | |
| Fabricantes | ON Semiconductor | |
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NB100LVEP224
2.5V/3.3V 1:24 Differential
ECL/PECL Clock Driver with
Clock Select and Output
Enable
Description
The NB100LVEP224 is a low skew 1−to−24 differential clock
driver, designed with clock distribution in mind, accepting two clock
sources into an input multiplexer. The part is designed for use in low
voltage applications which require a large number of outputs to drive
precisely aligned low skew signals to their destination. The two clock
inputs are differential ECL/PECL and they are selected by the
CLK_SEL pin. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE) is synchronous
ensuring the outputs will only be enabled/disabled when they are
already in LOW state (See Figure 4).
The NB100LVEP224 guarantees low output−to−output skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. In any differential output, the same bias and
termination scheme is required. Unused output pairs should be left
unterminated (open) to “reduce power and switching noise as much as
possible.” Any unused single line of a differential pair should be
terminated the same as the used line to maintain balancewdwwl.DoaatadShseeot4nU.ctohme
differential driver outputs. The wide VIHCMR specification allows
both pair of CLOCK inputs to accept LVDS levels.
The NB100LVEP224, as with most other ECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP224 to be used for high performance clock distribution in
+3.3 V or +2.5 V systems. Single−ended CLK input operation is
limited to a VCC ≥ 3.0 V in LVPECL mode, or VEE ≤ −3.0 V in NECL
mode. In a PECL environment, series or Thevenin line terminations
are typically used as they require no additional power supplies. For
more information on PECL terminations, designers should refer to
Application Note AND8020/D.
http://onsemi.com
MARKING
DIAGRAM*
LQFP−64
FA SUFFIX
CASE 848G
NB100
LVEP224
AWLYYWWG
64
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Features
• 20 ps Typical Output−to−Output Skew
• 75 ps Typical Device−to−Device Skew
• Maximum Frequency > 1 GHz
• 650 ps Typical Propagation Delay
• LVPECL Mode Operating Range:
VCC = 2.375 V to 3.8 V with VEE = 0 V
• NECL Mode Operating Range:
VCC = 0 V with VEE = −2.375 V to −3.8 V
• Internal Input Pulldown Resistors
• Q Output will Default Low with Inputs Open or at VEE
• Thermally Enhanced 64−Lead LQFP
• CLOCK Inputs are LVDS−Compatible; Requires
External 100 W LVDS Termination Resistor
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 7
1
Publication Order Number:
NB100LVEP224/D
1 page  
NB100LVEP224
Table 7. NECL DC CHARACTERISTICS VCC = 0 V, VEE = −2.375 V to −3.8 V (Note 11)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current VEE = −2.5 V 130 160 195 135 165 200 140 165 205 mA
VEE = −3.3 V 140 165 195 145 175 205 145 175 210
VOH Output HIGH Voltage (Note 12)
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV
VOL Output LOW Voltage (Note 12)
−1945 −1820 −1600 −1945 −1820 −1600 −1945 −1820 −1600 mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
(Note 13)
−880 −1165
−880 −1165
−880 mV
VIL
Input LOW Voltage (Single−Ended)
−1945
(Note 13)
−1600 −1945
−1600 −1945
−1600 mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 14) (Figure 5)
VEE + 1.2 0.0 VEE + 1.2 0.0 VEE + 1.2 0.0 V
IIH Input HIGH Current
IIL Input LOW Current
CLK 0.5
CLK −150
150
0.5
−150
150
0.5
−150
150 mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with VCC.
12. All outputs loaded with 50 W to VCC − 2.0 V.
13. Single ended input operation is limited VEE ≤ −3.0 V in NECL mode.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 8. AC CHARACTERISTICS VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 15)
−405C
255C
855C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOpp
Differential Output Voltage
(Figure 3)
fout < 50 MHz
fout < 0.8 GHz
fout < 1.0 GHz
600
600
600
750
750
700
600 725
600 725
525 650
575 700
550 650
400 525
mV
mV
mV
tPLH Propagation Delay (Differential Configuration)
tPHL CLKx−Qx 500 600 700 550 650 750 650 750 1000 ps
CLK_SELx−Qx 600 700 800 650 800 900 750 850 1150 ps
tskew
Within−Device Skew (Note 16)
Device−to−Device Skew (Note 17)
20 40
50 300
20 40
50 300
35 60
100 300
ps
ps
tJITTER
VPP
Random Clock Jitter (Figure 3) (RMS)
Input Swing (Differential Configuration)
(Note 19) (Figure 5)
15
15
1 5 ps
200 800 1200 200 800 1200 200 800 1200 mV
tS OE Set Up Time (Note 18)
tH OE Hold Time
tr/tf Output Rise/Fall Time
(20%−80%)
200 200 200
200 200 200
100 200 300 100 200 300 150 250 350
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
15. Measured with PECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC − 2 V.
16. Skew is measured between outputs under identical transitions and conditions on any one device.
17. Device−to−Device skew for identical transitions at identical VCC levels.
18. OE Set Up Time is defined with respect to the falling edge of the clock. OE High−to−Low transition ensures outputs remain disabled during
the next clock cycle. OE Low−to−High transition enables normal operation of the next input clock.
19. VPP is the differential input voltage swing required to maintain AC characteristics including tPD and device−to−device skew.
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