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83C152JC 데이터시트 PDF




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부품번호 83C152JC 기능
기능 UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER
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83C152JC 데이터시트, 핀배열, 회로
8XC152JA JB JC JD
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCONTROLLER
X 8K Factory Mask Programmable ROM Available
Y Superset of 80C51 Architecture
Y Multi-Protocol Serial Communication
I O Port (2 048 Mbps 2 4 Mbps Max)
SDLC HDLC Only
CSMA CD and SDLC HDLC
User Definable Protocols
Y Full Duplex Half Duplex
Y MCS -51 Compatible UART
Y 16 5 MHz Maximum Clock Frequency
Y Multiple Power Conservation Modes
Y 64KB Program Memory Addressing
Y 64KB Data Memory Addressing
Y 256 Bytes On-Chip RAM
Y Dual On-Chip DMA Channels
Y Hold Hold Acknowledge
Y Two General Purpose Timer Counters
Y 5 or 7 I O Ports
Y 56 Special Function Registers
Y 11 Interrupt Sources
Y Available in 48 Pin Dual-in-Line Package
and 68 Pin Surface Mount PLCC
Package
(See Packaging Spec Order 231369)
The 80C152 which is based on the MCS -51 CPU is a highly integrated single-chip 8-bit microcontroller
designed for cost-sensitive high-speed serial communications It is well suited for implementing Integrated
Services Digital Networks (ISDN) emerging Local Area Networks and user defined serial backplane applica-
tions In addition to the multi-protocol communication capability the 80C152 offers traditional microcontroller
features for peripheral I O interface and control
Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-to-
serial and serial-to-parallel converters The 83C152 contains in silicon all the features needed for the serial-
to-parallel conversion Other 83C152 benefits include 1) better noise immunity through differential signaling or
fiber optic connections 2) data integrity utilizing the stawnwdw.aDradtaShdeeets4Uig.cnomed in CRC checks and 3) better modulari-
ty of hardware and software designs All of these cost network parameter and real estate improvements
apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
October 1989
Order Number 270431-003




83C152JC pdf, 반도체, 판매, 대치품
8XC152JA JB JC JD
80C152JB JD General Description
The 80C152JB JD is a ROMless extension of the
80C152 Universal Communication controller The
80C152JB has the same five 8-bit I O ports of the
80C152 plus an additional two 8-bit I O ports Port 5
and Port 6 The 80C152JB JD also has two addi-
tional control pins EBEN (EPROM Bus ENable) and
EPSEN (EPROM bus Program Store ENable)
EBEN selects the functionality of Port 5 and Port 6
When EBEN is low these ports are strictly I O simi-
lar to Port 4 The SFR location for Port 5 is 91H and
Port 6 is 0A1H This means Port 5 and Port 6 are not
bit addressable With EBEN low all program memo-
ry fetches take place via Port 0 and Port 2 (The
80C152 is a ROMless only product) When EBEN is
high Port 5 and Port 6 form an address data bus
called the E-Bus (EPROM-Bus) for program memory
operations
EPSEN is used in conjunction with Port 5 and Port 6
program memory operations EPSEN functions like
PSEN during program memory operation but sup-
ports Port 5 and Port 6 EPSEN is the read strobe to
external program memory for Port 5 and Port 6
EPSEN is activated twice during each machine cycle
unless an external data memory operation occurs on
Port(s) 0 and Port 2 When external data memory is
accessed the second activation of EPSEN is
skipped which is the same as when using PSEN
Note that data memory fetches cannot be made
through Ports 5 and 6
When EBEN is high and EA is low all program mem-
ory operations take place via Ports 5 and 6 The high
byte of the address goes out on Port 6 and the low
byte is output on Port 5 ALE is still used to latch the
address on Port 5 Next the op code is read on Port
5 The timing is the same as when using Ports 0 and
2 for external program memory operations
Table 1 Program Memory Fetches
EBEN
EA
Program
Fetch via
PSEN
EPSEN
Comments
0
0
P0 P2
Active
Inactive
Addresses 0 – 0FFFFH
0 1 NA
N A N A Invalid Combination
1
0
P5 P6
Inactive
Active
Addresses 0 – 0FFFFH
1
1
P5 P6
Inactive
Active
Addresses 0 – 1FFFH
P0 P2
Active
Inactive
Addresses t 2000H
ROMless
Version
80C152JA
80C152JB
80C152JC
80C152JD
CSMA CD
and
HDLC SDLC
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Table 2 8XC152 Product Differences
HDLC SDLC
Only
ROM
Version
Available
PLCC
and
DIP
(83C152JA)
(83C152JC)
PLCC
Only
5I O
Ports
7I 0
Ports
NOTES
e options available
0 standard frequency range 3 5 MHz to 12 MHz
0 ‘‘b1’’ frequency range 3 5 MHz to 16 5 MHz
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83C152JC 전자부품, 판매, 대치품
8XC152JA JB JC JD
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of an inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 3
To drive the device from an external clock source
XTAL1 should be driven while XTAL2 is left uncon-
nected as shown in Figure 4 There are no require-
ments on the duty cycle of the external clock signal
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop but minimum and
maximum high and low times specified on the Data
Sheet must be observed
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts-up This is due
to interaction between the amplifier and its feedback
capacitance Once the external signal meets the VIL
and VIH specifications the capacitance will not ex-
ceed 20 pF
270431 – 6
Figure 4 External Clock Drive
IDLE MODE
In Idle Mode the CPU puts itself to sleep while most
of the on-chip peripherals remain active The major
peripherals that do not remain active during Idle are
the DMA channels The Idle Mode is invoked by
software The content of the on-chip RAM and all
the Special Function Registers remain unchanged
during this mode The Idle Mode can be terminated
by any enabled interrupt or by a hardware reset
POWER DOWN MODE
270431 – 5
Figure 3 Using the On-Chip Oscillator
In Power Down Mode the oscillator is stopped and
all on-chip functions cease except that the on-chip
RAM contents are maintained The mode Power
Down is invoked by software The Power Down
Mode can be terminated only by a hardware reset
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Table 3 Status of the External Pins During Idle and Power Down Modes
80C152JA 83C152JA 80C152JC 83C152JC
Mode
Idle
Idle
Power Down
Power Down
Program
Memory
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
Port 0
Data
Float
Data
Float
Port 1
Data
Data
Data
Data
Port 2
Data
Address
Data
Data
Port 3
Data
Data
Data
Data
Port 4
Data
Data
Data
Data
80C152JB 80C152JD
Mode
Instruction
Bus
ALE
PSEN
EPSEN
Port 0
Port 1
Port 2
Port 3 Port 4 Port 5
Port 6
Idle
P0 P2 1 1
1 Float Data Address Data Data 0FFH 0FFH
Idle
P5 P6 1 1
1 Data Data Data Data Data 0FFH Address
Power Down P0 P2 0 0
1 Float Data Data Data Data 0FFH 0FFH
Power Down P5 P6 0 1
0 Data Data Data Data Data 0FFH 0FFH
NOTE
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook and Application
Note AP-252 ‘‘Designing with the 80C51BH ’’
Note difference of logic level of PSEN during Power Down for ROM JA JC and ROM emulation mode for JC JD
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부품번호상세설명 및 기능제조사
83C152JA

UNIVERSAL COMMUNICATION CONTROLLER 8-BIT MICROCONTROLLER

Intel Corporation
Intel Corporation
83C152JA

Universal Communication Controller 8-Bit Microcontroller

Intel
Intel

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