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PDF ADCMP572 Data sheet ( Hoja de datos )
| Número de pieza | ADCMP572 | |
| Descripción | (ADCMP572 / ADCMP573) Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADCMP572 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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Ultrafast 3.3 V/5 V
Single-Supply SiGe Comparators
ADCMP572/ADCMP573
FEATURES
3.3 V/5.2 V single-supply operation
150 ps propagation delay
15 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
80 ps minimum pulse width
35 ps typical output rise/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)
On-chip terminations at both input pins
Robust inputs with no output phase reversal
Resistor-programmable hysteresis
Differential latch control
Extended industrial −40°C to +125°C temperature range
FUNCTIONAL BLOCK DIAGRAM
VCCI
VCCO
VTP TERMINATION
VP NONINVERTING
INPUT
VN INVERTING
INPUT
ADCMP572
ADCMP573
VTN TERMINATION
CML/
RSPECL
HYS
LE INPUT
LE INPUT
Figure 1.
Q OUTPUT
Q OUTPUT
APPLICATIONS
Clock and data signal restoration and level shifting
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
www.DataSheet4U.com
GENERAL DESCRIPTION
The ADCMP572 and ADCMP573 are ultrafast comparators
fabricated on Analog Devices’ proprietary XFCB3 Silicon
Germanium (SiGe) bipolar process. The ADCMP572 features
CML output drivers and latch inputs, and the ADCMP573
features reduced swing PECL (RSPECL) output drivers and
latch inputs.
Both devices offer 150 ps propagation delay and 80 ps
minimum pulse width for 10 Gbps operation with 200 fs rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 15 ps.
A flexible power supply scheme allows both devices to operate
with a single 3.3 V positive supply and a −0.2 V to +1.2 V input
signal range or with split input/output supplies to support a
wider −0.2 V to +3.2 V input signal range and an independent
range of output levels. 50 Ω on-chip termination resistors are
provided at both inputs with the optional capability to be left
open (on an individual pin basis) for applications requiring
high impedance inputs.
The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to between 3.3 V to 5.2 V.
The RSPECL output stage is designed to drive 400 mV into
50 Ω terminated to VCCO − 2 V and is compatible with several
commonly used PECL logic families. The comparator input
stage offers robust protection against large input overdrive, and
the outputs do not phase reverse when the valid input signal
range is exceeded. High speed latch and programmable
hysteresis features are also provided.
The ADCMP572 and ADCMP573 are available in a 16-lead
LFCSP package and have been characterized over an extended
industrial temperature range of −40°C to +125°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
SUPPLY VOLTAGE
Input Supply Voltage
(VCCI to GND)
Output Supply Voltage
(VCCO to GND)
Positive Supply Differential
(VCCI − VCCO)
INPUT VOLTAGE
Input Voltage
Differential Input Voltage
Input Voltage, Latch Enable
HYSTERESIS CONTROL PIN
Applied Voltage (HYS to GND)
Maximum Input/Output Current
OUTPUT CURRENT
ADCMP572 (CML)
ADCMP573 (RSPECL)
TEMPERATURE
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
Rating
−0.5 V to +6.0 V
−0.5 V to +6.0 V
−0.5 V to +3.5 V
−0.5 V to VCCI + 0.5 V
±(VCCI + 0.5 V)
−0.5 V to VCCO + 0.5 V
−0.5 V to +1.5 V
±1 mA
±20 mA
−35 mA
−40°C to +125°C
+150°C
−65°C to +150°C
ADCMP572/ADCMP573
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
THERMAL CONSIDERATIONS
The ADCMP572/ADCMP573 LFCSP 16-lead package has a θJA
(junction-to-ambient thermal resistance) of 70°C/W in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 16
5 Page 
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a
noisy environment or when the differential input amplitudes are
relatively small or slow moving, but excessive hysteresis has a
cost in degraded accuracy and slew-induced timing shifts. The
transfer function for a comparator with hysteresis is shown in
Figure 19. If the input voltage approaches the threshold (0.0 V
in this example) from the negative direction, the comparator
switches from low to high when the input crosses +VH/2. The
new switching threshold becomes −VH/2. The comparator
remains in the high state until the threshold −VH/2 is crossed
from the positive direction. In this manner, noise centered on
0.0 V input does not cause the comparator to switch states
unless it exceeds the region bounded by ±VH/2.
OUTPUT
VOH
VOL
0
–VH
2
INPUT
+VH
2
Figure 19. Comparator Hysteresis Transfer Function
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. A limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that can be load dependent and is not symmetrical
about the threshold. The external feedback network can also
introduce significant parasitics, which reduce high speed
performance and can even induce oscillation in some cases.
The ADCMP572/ADCMP573 comparators offer a program-
mable hysteresis feature that can significantly improve the
accuracy and stability of the desired hysteresis. By connecting
an external pull-down resistor from the HYS pin to GND, a
variable amount of hysteresis can be applied. Leaving the HYS
pin disconnected disables the feature, and hysteresis is then less
than 1 mV as specified. The maximum hysteresis that can be
applied using this method is approximately ±25 mV with the
pin grounded. Figure 20 illustrates the amount of hysteresis
ADCMP572/ADCMP573
applied as a function of external resistor value. The advantages
of applying hysteresis in this manner are improved accuracy,
stability, and reduced component count. An external bypass
capacitor is not recommended on the HYS pin because it would
likely degrade the jitter performance of the device. The
hysteresis pin could also be driven by a CMOS DAC. It is biased
to approximately 250 mV and has an internal series resistance
of 600 Ω.
60
50
40
30
20
10
0
01 23456
RHYS (kΩ)
Figure 20. Hysteresis vs. RHYS Control Resistor
MINIMUM INPUT SLEW RATE REQUIREMENTS
As with all high speed comparators, a minimum slew rate
requirement must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This
oscillation is due in part to the high input bandwidth of the
comparator and the feedback parasitics inherent in the package.
A minimum slew rate of 50 V/µs should ensure clean output
transitions from the ADCMP572/ ADCMP573 comparators.
The slew rate may be too slow for other reasons. The extremely
high bandwidth of these devices means that broadband noise
can be a significant factor when input slew rates are low. There
will be at least 120 µv of thermal noise generated over the full
comparator bandwidth by two 50 Ω terminations at room
temperature. With a slew rate of only 50 V/µs the input will be
inside this noise band for over 2 ps, rendering the comparator’s
jitter performance of 200 fs moot. Raising the slew rate of the
input signal and/or reducing the bandwidth over which this
resistance is seen at the input can greatly reduce jitter.
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADCMP572.PDF ] | |
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