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ADCMP573 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADCMP573은 전자 산업 및 응용 분야에서
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부품번호 ADCMP573 기능
기능 (ADCMP572 / ADCMP573) Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators
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ADCMP573 데이터시트, 핀배열, 회로
Ultrafast 3.3 V/5 V
Single-Supply SiGe Comparators
ADCMP572/ADCMP573
FEATURES
3.3 V/5.2 V single-supply operation
150 ps propagation delay
15 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
80 ps minimum pulse width
35 ps typical output rise/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)
On-chip terminations at both input pins
Robust inputs with no output phase reversal
Resistor-programmable hysteresis
Differential latch control
Extended industrial −40°C to +125°C temperature range
FUNCTIONAL BLOCK DIAGRAM
VCCI
VCCO
VTP TERMINATION
VP NONINVERTING
INPUT
VN INVERTING
INPUT
ADCMP572
ADCMP573
VTN TERMINATION
CML/
RSPECL
HYS
LE INPUT
LE INPUT
Figure 1.
Q OUTPUT
Q OUTPUT
APPLICATIONS
Clock and data signal restoration and level shifting
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
www.DataSheet4U.com
GENERAL DESCRIPTION
The ADCMP572 and ADCMP573 are ultrafast comparators
fabricated on Analog Devices’ proprietary XFCB3 Silicon
Germanium (SiGe) bipolar process. The ADCMP572 features
CML output drivers and latch inputs, and the ADCMP573
features reduced swing PECL (RSPECL) output drivers and
latch inputs.
Both devices offer 150 ps propagation delay and 80 ps
minimum pulse width for 10 Gbps operation with 200 fs rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 15 ps.
A flexible power supply scheme allows both devices to operate
with a single 3.3 V positive supply and a −0.2 V to +1.2 V input
signal range or with split input/output supplies to support a
wider −0.2 V to +3.2 V input signal range and an independent
range of output levels. 50 Ω on-chip termination resistors are
provided at both inputs with the optional capability to be left
open (on an individual pin basis) for applications requiring
high impedance inputs.
The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to between 3.3 V to 5.2 V.
The RSPECL output stage is designed to drive 400 mV into
50 Ω terminated to VCCO − 2 V and is compatible with several
commonly used PECL logic families. The comparator input
stage offers robust protection against large input overdrive, and
the outputs do not phase reverse when the valid input signal
range is exceeded. High speed latch and programmable
hysteresis features are also provided.
The ADCMP572 and ADCMP573 are available in a 16-lead
LFCSP package and have been characterized over an extended
industrial temperature range of −40°C to +125°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.




ADCMP573 pdf, 반도체, 판매, 대치품
ADCMP572/ADCMP573
Parameter
Symbol
Conditions
Min Typ Max Unit
AC PERFORMANCE
Propagation Delay
tPD VCCI = 3.3 V, VOD = 200 mV
150
ps
VCCI = 3.3 V, VOD = 20 mV 165 ps
VCCI = 5.2 V, VOD = 200 mV 145 ps
Propagation Delay Tempco
∆tPD/dT
0.5 ps/°C
Prop Delay Skew—Rising Transition
to Falling Transition
VOD = 200 mV, 5 V/ns
10 ps
Overdrive Dispersion
50 mV < VOD < 0.2 V, 5 V/ns
15
ps
10 mV < VOD < 0.2 V, 5 V/ns
15
ps
Slew Rate Dispersion
2 V/ns to 10 V/ns, 250 mV OD
15
ps
Pulse Width Dispersion
100 ps to 5 ns, 250 mV OD
5
ps
10% – 90% Duty Cycle Dispersion
VCCI = 3.3 V, 1 V/ns, 250 mV OD
5
ps
VCCI = 5.2 V, 1 V/ns, 250 mV OD
10
Common-Mode Dispersion
Equivalent Input Bandwidth1
BWEQ
VOD = 0.2V, 0.0 V < VCM < 2.9 V
0.0 V to 250 mV input
tR = tF = 17 ps, 20/80
5
8.0
ps/V
GHz
Toggle Rate
>50% Output Swing
12.5 Gbps
Deterministic Jitter
DJ VOD = 200 mV, 5 V/ns,
10 ps
PRBS31 − 1 NRZ, 4 Gbps
VOD = 200 mV, 5 V/ns,
PRBS31 − 1 NRZ, 10 Gbps
20
ps
RMS Random Jitter
RJ VOD = 200 mV, 5 V/ns, 1.25 GHz
0.2
ps
Minimum Pulse Width
PWMIN
∆tPD/∆PW < 5 ps, 200 mV OD
100
ps
PWMIN
∆tPD/∆PW < 10 ps, 200 mV OD
80
ps
Rise Time
tR 20/80
35 ps
Fall Time
tF 20/80
35 ps
POWER SUPPLY
Input Supply Voltage Range
VCCI
3.1 5.4 V
Output Supply Voltage Range
VCCO
3.1 5.4 V
Positive Supply Differential
VCCI −VCCO
−0.2 +2.3 V
ADCMP572 (CML)
Positive Supply Current
IVCCI + IVCCO
VCCI = 3.3 V, VCCO = 3.3 V,
terminate 50 Ω to VCCO
44 52 mA
VCCI = 5.2 V, VCCO = 5.2 V,
terminate 50 Ω to VCCO
44 52
Device Power Dissipation PD VCCI = 3.3 V, VCCO = 3.3 V,
terminate 50 Ω to VCCO
140 165 mW
VCCI = 5.2 V, VCCO = 5.2 V,
terminate 50 Ω to VCCO
230 265
ADCMP573 (RSPECL)
Positive Supply Current
IVCCI + IVCCO
VCCI = 3.3 V, VCCO = 3.3 V,
50 Ω to VCCO − 2 V
62 80 mA
VCCI = 5.2 V, VCCO = 5.2 V,
50 Ω to VCCO − 2V
64 80
Device Power Dissipation PD VCCI = 3.3 V, VCCO = 3.3 V,
50 Ω to VCCO − 2 V
110 160 mW
VCCI = 5.2 V, VCCO = 5.2 V,
50 Ω to VCCO − 2 V
146 230
1 Equivalent input bandwidth assumes a simple first-order response and is calculated with the following formula: BWEQ = 0.22/(trCOMP2−trIN2), where trIN is the 20/80
transition time of a quasi-Gaussian signal applied to the comparator input, and trCOMP is the effective transition time digitized by the comparator.
Rev. 0 | Page 4 of 16

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ADCMP573 전자부품, 판매, 대치품
TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 3.3 V, TA = 25°C, unless otherwise noted.
20
15
10
5
0
0 50 100 150 200 250
INPUT OVERDRIVE VOLTAGE (mV)
Figure 3. Propagation Delay vs. Input Overdrive
158.5
158.0
157.5
157.0
156.5
156.0
155.5
0
0.2 0.4 0.6 0.8 1.0
INPUT COMMON-MODE VOLTAGE (V)
1.2
Figure 4. Propagation Delay vs. Input Common-Mode
160
158
156
154
152
150
148
146
–60
–40 –20
0
20 40 60
TEMPERATURE (°C)
80
Figure 5. Propagation Delay vs. Temperature
100
ADCMP572/ADCMP573
39.0
38.5
38.0
37.5
37.0
36.5
36.0
–60
–40 –20
0
20 40 60
TEMPERATURE (°C)
80
Figure 6. Rise/Fall Time vs. Temperature
100
60
50
40
30
20
10
0
01 23456
RHYS (k)
Figure 7. Hysteresis vs. RHYS Control Resistor
80
70
60
50
40
30
20
10
0
–600
–500
–400
–300
–200
RHYS SINK CURRENT (µA)
–100
Figure 8. Hysteresis vs. RHYS Sink Current
0
Rev. 0 | Page 7 of 16

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